Xilinx, Inc.

Azarudin Abdulla

Riyas Noorudeen Remla

Chee Chong Chan

Gourav Modi

Examples described herein provide a method for reducing lane-to-lane serial skew in an integrated circuit. In an example using a processor-based system, a maximum clock skew is determined from clock skews of respective lanes of a transmitter of the IC. Each of the clock skews corresponds to a skew of a clock signal of the respective lane relative to a same reference clock signal. A skew match amount is determined for each lane of the lanes of the transmitter. The skew match amount for a respective lane of the lanes is based on the maximum clock skew and the clock skew of the respective lane. Configuration data is generated to configure the transmitter to shift incoming data for each lane of the lanes based on the skew match amount for the respective lane.

Serial lane-to-lane skew reduction

Apparatus and associated methods relate to a dynamic lane-to-lane skew reduction technique having (a) a clocking architecture configured to provide a corresponding first delayed clock signal and a corresponding second delayed clock signal through a first and a second plurality of routing traces, respectively, and (b) a number of skew compensation circuits configured to process the corresponding first delayed clock signal and the corresponding second delayed clock signal to generate a corresponding user clock signal for a corresponding lane of a transmitter. In an illustrative example, a first routing trace may transmit a first delayed clock signal in a direction opposite to a second routing trace transmitting a second delayed clock signal. By implementing the technique, each transmitter lane may receive a corresponding user clock signal having substantially the same delay relative to a reference clock signal such that dynamic lane-to-lane skew may be advantageously reduced.

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Singapore, Singapore

Azarudin Abdulla