L-3 Communications Corporation

Unisys Corporation

Ayyoob Dehgani Abbaszadeh

Ryan W Hinton

David G Landon

Eric K Hall

Thomas R Giallorenzi

Richard B Ertel

Merle LeRoy Keller, Jr

Robert J Currie

Craig K Rushforth

Dale D Fonnesbeck

Kelly D Griffiths

Rahman Altaf

David Todd Wilstead

Altaf Rahman

A permutation apparatus can receive a data block of ordered data elements in parallel data segments that are Pnumber of data elements wide. The permutation apparatus can perform a parallel-to-parallel conversion and one or more reorder operations on the data elements and output the data block in parallel data segments that are Pnumber of data elements wide and in which at least some of the data elements are reordered. The P-parallel-data segments can be clocked into the permutation apparatus on successive cycles of a clock, and the P-parallel-data segments can be clocked out of the permutation apparatus on cycles of the same clock.

Parallel-to-parallel conversion and reordering of a block of data elements

A decoder for decoding received vectors r encoded in accordance with a forward error correction code having a parity check matrix H with multiple regions at least two of which have patterns of ones with different pattern characteristics. The decoder can include a permuted decode module configured to decode in accordance with a permuted version of the parity check matrix H in which the ones in one of the regions are permuted into a permuted pattern that has a pattern characteristic of the other region. The decoder can also include a reorder module that permutes probabilities of a received vector r to be decoded to correspond with the permuted parity check matrix H.

Decoding vectors encoded with a linear block forward error correction code having a parity check matrix with multiple distinct pattern regions

A symbol de-mapper can determine soft values for the bits of a complex symbol R that has been transmitted and received at a receiving device. The symbol de-mapper can reduce the number of calculations needed to determine soft values of the bits by limiting the symbols S utilized to calculate the soft values to subsets of the symbols S associated with sectors of symbol rings in the symbol constellation.

Complex symbol de-mapping using sectoring

A technique for decoding low-density parity check codes includes performing a combined check node and variable node calculation. Decoding is initialized using channel likelihood values estimated from a received physical signal. The decoding iteratively updates the variable nodes. Performing a combined check node and variable node calculation can enable reduced memory usage and faster convergence for the decoder.

Low-density parity check decoding using combined check node and variable node

A source controller provides a block of n&#xd7;a information bits as n separate rows each with a information bits. A row encoder has an input coupled to an output of the source controller and includes a plurality of accumulators arranged to process m of the information bits in one clock cycle to generate row forward error correction FEC bits. At least one column encoder has an input coupled to an output of the source controller and is arranged to generate column FEC bits in parallel with the row encoder. A multiplexer is coupled to outputs of the row and column encoders and is adapted to serially output an nrow of information bits followed by the nrow FEC bits for each of the n rows, followed by additional rows of FEC bits generated by the column encoder. The terms n, m, and a are integers greater than one. Where more than one column encoder is used, there are preferably m column encoders in parallel and each operating at one bit per clock cycle.

High data throughput turbo product encoder

A system and method for parallel Pseudo-random Noise (PN) code generation is disclosed. The method includes the operation of producing a PN code sequence having a predetermined length. The PN code can be divided into L segments. At least one of the L segments can have a length less than other segments. The L segments can be distributed into an array of L digital memories. Each of the digital memories can output every Lth chip of the PN code in parallel at a selected rate. An element of the PN code can be substituted from an element substitution cache into the output of the L digital memories to compensate for segment(s) having a shorter length.

System and method for memory-based parallel PN generation

Method and apparatus are disclosed for obtaining improved performance when using Forward Error Correction (FEC) with channels experiencing block fading or burst jamming over some number of contiguous symbols. One suitable application is when the channel is periodically obstructed due to the rotation of a propeller blade, resulting in a periodic block fading channel. During operation zero symbols are inserted into the received signal stream, prior to the FEC decoder at times that are estimated or otherwise determined to correspond to periods of jamming or severe fading. The zero symbols effectively 'erase' the severely degraded symbols. The zero symbols are less detrimental to the FEC decoder than the severely degraded symbols, especially when the channel interleaving/de-interleaving operations result in the zero symbols being temporarily distributed over a large block of received symbols.

Digital communications method and system for communicating over channels with block fading and burst jamming

A technique for resolving access contention in a parallel turbo decoder is described. The technique includes associating a plurality of buffer memories with the subdecoders so that accesses to banks of a shared interleaver memory can be rescheduled. Accesses can be rescheduled to prevent simultaneous accesses to a single bank of the shared interleaver memory based on an interleaver pattern.

Memory arbitration technique for turbo decoding

The invention provides a system and method for generating a high rate pseudo-random noise (PN) code with a parallel PN generator. The method includes the operation of configuring L programmable PN generators to each output every Lchip of a PN code. Select PN generators of the L PN generators can be configured to have their output delayed for a predetermined number of chips less than or equal to L when a fine slip is needed to allow the high rate PN code to be delayed for a set number of chips to synchronize the high rate PN code with another PN code. The outputs of each of the L programmable PN generators can be multiplexed to produce the high rate PN code.

System and method for parallel PN generation

A block sliding window data decoder includes a forward recursion calculator and a plurality of backward recursion calculators including a first backward recursion calculator and a second backward recursion calculator that receives inputs from the first backward recursion calculator. The first backward recursion calculator operates every D cycles to perform a backward recursion over received input signals, while assuming that all future states are equally likely. The decoder further includes a symbol probability calculator that receives inputs from the forward recursion calculator and from the first backward recursion calculator. A memory of the decoder stores the input signals and is organized as N cells, wherein for each cycle one of the N cells is written while N&minus;1 of the cells are read and their contents provided to the forward recursion calculator and to the first and second backward recursion calculators. Each calculation cell of the decoder includes a normalizer for normalizing the input signal and signals processed by the forward recursion calculator and the first and second backward recursion calculators. The normalizer is implemented using AND functions.

Simplified block sliding window implementation of a map decoder

A method of branch metric calculation of trellis coded data, suitable for a decoder of phase angle on a carrier modulated with phase shift keying (PSK) modulation, begins with an expressing angles of phase shift by a vectorial representation of sectors within quadrants of a circle. The sectors are subdivided into sub-sectors of differing sizes, and the sub-sectors are divided further into equal increments of angle referred to as PIEs. The PIEs and the quadrants are identified and, in each quadrant, there is an assigning of a set of branch metrics to serve as identifiers of respective ones of the sub-sectors in each sector of the quadrant. The set of branch metrics in one sector of the quadrant differs from the set of branch metrics in another of the sectors of the quadrant by a permutation of the branch metrics. The phase data is outputted in the form of branch metrics and quadrant for use by a decoder such as a Viterbi decoder.

Simplified branch metric calculation in pragmatic trellis decoders

A system including coding and decoding circuits provides for resolution of the phase ambiguities in pragmatic trellis-coded PSK modulation transmissions. An error correcting coder, such as a convolutional encoder, precedes the modulator for reducing the effect of noise in inducing phase errors. A corresponding decoder appears at the reception end of the communication system. A differential encoder and decoder automatically remove the possible phase ambiguities, and operate in conjunction with the error correcting encoder and decoder. Each of the ambiguity-removal differential encoder and the decoder act as an operator upon its input signal. In order that both the error correcting encoder and the ambiguity encoder immediately precede the modulator, the ambiguity removal circuitry is placed between the error correcting encoder, and is constructed as a combination of differential encoder and inverse differential encoder. The use for ambiguity removal of both the differential encoder and the inverse differential encoder operates to remove the phase ambiguity while making the ambiguity operation transparent to the output of the error correction encoder. This retains the benefit of placing the error correcting encoder immediately before the modulator.

Differential codec for pragmatic PSK TCM schemes

A novel maximum likeihood decoder for the Golay (24,12) code is provided. Instead of decoding the received dimensional vector (X) is a systolic array, the vector is mapped into a (24,5) subcode with an index 128 which is easily decoded. The decoder employs a plurality of precomputational circuits cooperating with a similar plurality of inner product circuits which compute the 128 inner product values and select the maximum inner product value from each inner product circuit. The maximum inner product value from each circuit is loaded into a select logic circuit for selecting the maximum inner product value and its corresponding code word closest to the received vector (X).

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Salt Lake City, UT, United States of America

Ayyoob Dehgani Abbaszadeh