Nec Corporation

Tohoku University

Nanobridge Semiconductor, Inc.

Nec C Orporation

Nec Electronics Corporation

Ayuka Tada

Ryusuke Nebashi

Yukihide Tsuji

Makoto Miyamura

Xu Bai

Toshitsugu Sakamoto

Noboru Sakimura

Hideo Ohno

Tadahiko Sugibayashi

Tetsuo Endoh

Munehiro Tada

Kiyotaka Imai

Hirohito Watanabe

Naohiko Kimizuka

Takahiro Hanyu

Motofumi Saitoh

Hiroaki Honjou

Toshiyuki Iwamoto

Yuri Masuoka

A numerical information generating apparatus receives information of a programmable logic integrated circuit that includes a plurality of crossbar switches each including resistance change elements, calculates, for each of the plurality of crossbar switches, a base delay that is a delay in which influence of a load capacitance of other crossbar switch is excluded and a correction delay that is a delay caused by influence of a fanout of other crossbar switch, and further calculates a delay of each of the plurality of crossbar switches based on the base delay and the correction delay corresponding to each of the plurality of crossbar switches.

Numerical information generation apparatus, numerical information generation method, and program

In order to eliminate an increase in the source potential of a transistor selected during writing or reading, this semiconductor device is equipped with: a variable-resistance type first switch having a first terminal and a second terminal; a variable-resistance type second switch having a third terminal and a fourth terminal, the third terminal being connected to the second terminal to form an intermediate node; first wiring connected to the first terminal; second wiring connected to the fourth terminal and, in a planar view, extending in a direction crossing the first wiring; a first selection transistor connected to the first wiring; a second selection transistor connected to the second wiring; a first well terminal connection line to which a well terminal of the first selection transistor is connected; and a second well terminal connection line to which a well terminal of the second selection transistor is connected.

Semiconductor device

A reconfigurable circuit includes: a first line; a first switch element disposed between the first line and a first power source line of first voltage; a second line; a second switch element disposed between the second line and a second power source line of second voltage which is different from the first voltage; and a resistive switch assembly disposed between the first line and the second line. The resistive switch assembly includes: a first non-volatile resistive switch; and a second non-volatile resistive switch whose first end is coupled to a first end of the first non-volatile resistive switch. The second end of the first non-volatile resistive switch is coupled to the first line, and the second end of the second non-volatile resistive switch is coupled to the second line.

Reconfigurable circuit and the method for using the same

A logic integrated circuit includes a switch cell array. The switch cell array includes: a plurality of first wirings extending in a first direction; a plurality of second wirings extending in a second direction; a switch cell including a unit element including two serially connected resistance-changing elements, and a cell transistor to be connected to a shared terminal of the two resistance-changing elements; and a bit line to which the shared terminal is connected via the cell transistor. Two of the switch cells adjacent to each other in the first direction are each connected to the different first wiring and second wiring, and share the bit line, and a diffusion layer to which the bit line is connected.

Logic integrated circuit

A reconfigurable circuit includes: a plurality of first lines; one or more second lines; a non-volatile resistive cell coupling one of the first lines with one of the second lines at each cross-point between the first lines and the second lines; and first switch elements including first terminals respectively coupled to the first lines, wherein each of the first switch elements is separately turned on or off in accordance with a control signal applied thereto.

Reconfigurable circuit using nonvolatile resistive switches

A reconfigurable circuit comprising: crossbar switches; wires, each of which is coupled to one output port of one crossbar switch and input ports of the other crossbar switches; at least one inverter inserted on each wire for driving long-distance signal transfer, wherein one or less first inverter is inserted on the wire between two adjacent crossbar switches; one or two second inverters inserted between a crossbar switch input port and its connected wire.

Routing network for reconfigurable circuit

A logic integrated circuit includes: a three-terminal resistance change switch including a first resistance change switch and a second resistance change switch connected in series; a reading circuit which reads first data based on a resistance state of the first resistance change switch and second data based on a resistance state of the second resistance change switch; and a first error detection circuit which compares the first data with the second data and issue an output based on a result of the comparison.

Logic integrated circuit and semiconductor device

In order to provide a highly reliable crossbar circuit that enables salvation of reversal of a resistive state of a variable resistance element, the semiconductor device has a configuration obtained by parallelly arranging two unit elements, each including variable-resistance two-terminal elements connected in series, the semiconductor device being provided with: a unit element group being connected to a first wiring and a second wiring; a first programming driver that changes, via the first wiring, a resistive state of the two-terminal element constituting the unit element group; a first selection transistor being connected to the first wiring and the first programming driver; a second programming driver that changes, via the second wiring, a resistive state of the two-terminal element constituting the unit element group; and a second selection transistor being connected to the second wiring and the second programming driver.

Semiconductor device and programming method therefor

Provided is a programmable logic integrated circuit wherein even if a failure occurs in any resistance-variable element, remedy would be possible and hence the improvement of reliability has been achieved. In a programmable logic integrated circuit comprising resistance-variable elements, when the states of the resistance-variable elements are to be changed according to externally inputted configuration information, a control means uses a reading means to read the states of the respective resistance-variable elements, and then uses a writing means to change only the states of resistance-changing elements that are different from a state indicated by the configuration information.

Programmable logic integrated circuit, design support system, and configuration method

Provided is an integrated circuit that has reduced power consumption. The integrated circuit is provided with: a plurality of first wires one end of each of which is used as an input terminal; a plurality of second wires one end of each of which is used as an output terminal and which are respectively connected to the first wires; a bias wire which is connected to each of the second wires, and which is connected to a power supply or ground; a plurality of switches which connect the first wires or the bias wire and the second wires; and a selection circuit which selects electrical connection between the bias wire and the power supply or ground.

Integrated circuit

A reconfigurable circuit includes first and second wires and two or more paths active at different times. Each path includes: a first NVRS whose first terminal is connected to the first wire; a first transistor whose drain terminal is connected to a second terminal of the first NVRS; a second NVRS whose first terminal is connected to the second terminal of the first NVRS; a second transistor whose source terminal is connected to a second terminal of the second NVRS and whose drain terminal is connected to the second wire; and a 2-input AND circuit whose output is connected to a gate terminal of the first transistor. A time control signal is supplied to a first input of the 2-input AND circuit and a gate terminal of the second transistor. A write control signal is supplied to a second input of the 2-input AND circuit.

Reconfigurable circuit

An object of the present invention is to provide a method for effectively performing characterization for circuit verification by static timing analysis, of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein: the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch; the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell; and circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.

Programmable logic integrated circuit, semiconductor device, and characterization method

A reconfigurable circuit comprising: a first level crossbar switch that has first non-volatile resistive switches; a second level crossbar switch that has second non-volatile resistive switches; and a first wire and third non-volatile resistive switches that are used for redundancy, wherein input wires of the second level crossbar switch are connected to output wires of the first level crossbar switch one-to-one, and input wires of the first level crossbar switch and output wires of the second level crossbar switch are connected to the first wire through the third non-volatile resistive switches.

Reconfigurable circuit with crossbar switches including non-volatile resistive switches

In order to stably write data into a magnetic memory that uses in-plane current-induced perpendicular switching of magnetization to write data, the magnetic memory includes a recording layer formed as a perpendicular magnetization film, an adjacent layer joined to an upper surface or a lower surface of the recording layer, an external magnetic field application part configured to apply a first external magnetic field to the recording layer in a first direction which is an in-plane direction of the recording layer, and a current application part configured to allow a write current to flow through the adjacent layer in the first direction or a second direction which is opposite to the first direction. The external magnetic field application part is configured to switch a direction of a second external magnetic field applied in a direction perpendicular to the first direction in accordance with a direction of the write current.

Magnetic memory and method for writing data into magnetic memory element

A semiconductor integrated circuit () comprising: a plurality of processing circuits () each including a notification units for outputting a notification signal according to the processing state of the own processing circuit; a plurality of power supply switch units (SW, SW, SW) for switching the connection states between the respective processing circuits and a power supply source; a power supply switch control circuit which is connected with the notification means (), stores power supply control information () including a plurality of connection statuses, and controls the connection states on the basis of the notification signals and the power supply control information; and a data bus (BS) and the like connecting each of the processing circuits and the power supply switch control circuit, wherein: at least two or more of the plurality of processing circuits update the power supply control information via the data bus and the like before outputting a notification signal; and the power supply switch control circuit accepts a notification signal outputted from any one of the plurality of processing circuits after the update, and accordingly controls the connection states of respective ones of the plurality of power supply switch units on the basis of the updated power supply control information.

Growing community of inventors

Tokyo, Japan

Ayuka Tada