Intel Corporation

Tahoe Research, Ltd.

Aymen Zayet

Rajeev D Muralidhar

Harinarayanan Seshadri

Youvedeep Singh

Richard Quinzio

Christophe Fiat

Vishwesh M Rudramuni

Illyas M Mansoor

Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

Platform power consumption reduction via power state switching

Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., Six) instead of a second low power consumption state (e.g., S) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

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Antibes, France

Aymen Zayet