Mediatek Singapore Pte. Ltd.

Mediatek Corporation

Ayman Shabra

Michael Anthony Ashburn, Jr

Aiguo Yan

Stacy Ho

Halil Kiper

Patrick Cooney

Adalberto Cantoni

Joshua M Bamford

Described herein are DACs with low distortion for high dynamic range (HDR), extremely high dynamic range (EHDR), and other suitable applications. Some embodiments relate to a device including a DAC configured for coupling to an amplifier via a force path and a sense path. For example, the DAC may provide output current to the amplifier via the force path, and the DAC may sense the input voltage of the amplifier via the sense path. Accordingly, distortion such as harmonic distortion and/or gain offset from parasitic impedances in the force and/or sense paths may be reduced or eliminated. Some embodiments relate to a DAC including a voltage reference generator configured to compensate for variations in impedances of the DAC, such as due to semiconductor process variation. Accordingly, distortion in the DAC output due to variations in the DAC impedances may be reduced or eliminated.

Resistive DAC with summing junction switches, current output reference, and output routing methods

Circuits and methods for converting digital input signals into the analog domain are described. Such circuits may perform the conversion in a segmented fashion. For example, a circuit may include a most significant bit (MSB) path and a least significant bit (LSB) path. The MSB path may include a first delta-sigma modulator having first and second outputs and a first digital-to-analog converter coupled to the first output of the first delta-sigma modulator. The LSB path comprises a second delta-sigma modulator comprising a loop filter and a quantizer. The quantizer may have an input coupled to the loop filter and to the digital filter. The LSB path may further include a second digital-to-analog converter coupled to an output of the quantizer. The circuit may further include a digital filter and/or a gain stage interposed between the MSB path and the LSB path.

Methods and circuits for suppressing quantization noise in digital-to-analog converters

A comparator is described. The comparator may be used in several applications, including in digital-to-analog converters (ADC). The comparator may comprise a high-speed amplifier, a low-noise amplifier, a controller and a bi-stable circuit. The high-speed amplifier may be activated during a first period, for example when the comparator tends to exhibit a slow response. During this period, the comparator may sacrifice the noise performance. The low-noise amplifier may be activated during a second period, for example when the difference between the signals appearing as inputs to the comparator is small. The low-noise amplifier may have a gain that is large enough to limit decision errors. The bi-stable circuit, which may be implemented using a latch, may be configured to output a signal equal to one of the supply voltages, in response to receiving the input signal from one of the stages.

Comparator having a high-speed amplifier and a low-noise amplifier

A continuous-time sigma-delta analog-to-digital converter includes a plurality of integrator stages, in which one of the integrator stages includes a current buffer that drives an integrating capacitor. The analog-to-digital converter includes an outer feedback digital-to-analog converter and an inner digital-to-analog converter. The inner digital-to-analog converter is a current-mode digital-to-analog converter that converts the digital output signal to an analog current feedback signal, which is provided to an output of the integrator stage that includes the current buffer. Both the analog current feedback signal and an input signal provided to the current buffer are integrated by the integrating capacitor.

Direct feedback for continuous-time oversampled converters

A reconfigurable analog-to-digital (ADC) modulator structure that includes a plurality of ADC structures being coupled to each other through their respective noise quantization transfer functions. Each ADC structure receives as input an analog signal and each ADC structure outputting a plurality of first output signals. An adder module receives the first output signals and performs addition on the first output signals and generates a second output signal. A division module receives the second output signal and performs division on the second output signal by a predetermined factor.

Reconfigurable delta-sigma modulator ADC using noise coupling

The invention relates to a cascaded scheme in which an RRC filter, a modified RRC filter or other digital filter is implemented at a relatively low data rate, such as twice the symbol or chip rate, or 2&#xd7;. Interpolation filters are used to increase the data rate to a higher data rate, such as 8&#xd7;. Decimation filters are used to reduce the data rate from a higher rate, such as 8&#xd7;, to a lower rate, such as 2&#xd7;. The coefficients of the digital filter may be adjusted to compensate for characteristics of other components across the entire filter chain. Most of the implementation complexity of the filter chain is consolidated into the relatively low rate (such as 2&#xd7;) digital filter while interpolation or decimation filters can be implemented at very low cost. The compensation capability provided by the digital filter makes design of simple decimation or interpolation filters much easier. The compensation capability provided by the digital filter, along with the relatively high over-sampling rate for the output of the interpolation filter (or the input of the decimation filter), also makes the design of the preceding (or following) analog filters much easier.

Filters for communication systems

A multi-input-multi-output-system (MIMO) is provided that includes a first input signal and a second input signal. A plurality of analog-to-digital converter (ADC) cell structures receive as input a combination of the first input signal and the second input signal as well as a combination of quantization noise signals from the respective other ADC cell structures of the plurality of ADC cell structures. The ADC cell structures generate a plurality of first output signals and the noise quantization signals. A plurality of adder modules receive the first output signals and performing either addition or subtraction on a selected combination of the first output signals, the adder modules generate a plurality of second output signals. A plurality of division modules receive the second output signals and perform a division operation on the second output signals by a predetermined factor. The division modules generate a plurality of final output signals of the MIMO.

MIMO delta-sigma delta analog-to-digital converter using noise canceling

An integrated circuit comprises a threshold generation circuitry for generating at least one differential voltage signal. The threshold generation circuitry comprises at least one common mode current generation circuit arranged to generate at least one common mode current signal, whereby said at least one common mode current signal is combined with at least one input current signal to produce a combined current signal comprising a combined signal common mode component. Conversion circuitry is arranged to receive the combined current signal and convert the combined current signal into the at least one differential voltage signal for use within the comparator circuit. The threshold generation circuitry further comprises feedback circuitry arranged to receive an indication of the combined signal common mode component, compare the received indication to a reference value, and regulate the at least one common mode current signal based at least partly on the comparison results.

Integrated circuit and electronic device comprising threshold generation circuitry and method therefor

A method is disclosed for providing a digital filter system for providing a low pass filter function to a digital input. The method includes the steps of determining a finite impulse response of the input, determining a transfer function of the finite impulse response and providing a polynomial, identifying a plurality of stopband roots of the polymonial that lie in a complex plane, identifying real and complex conjugate pairs for the plurality of stopband roots, and providing coefficients for a complex polynomial that realizes the real and complex conjugate pairs such that a plurality of adjusted stopband roots lie on a unit circle of said complex plane.

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Woburn, MA, United States of America

Ayman Shabra