Cadence Design Systems, Inc.

Ayman Hanna

Habeeb Farah

Thiago Radicchi Roque

Doron Bustan

Karam Abdelkader

Felipe Althoff

A method for sequential equivalence checking (SEC) of two representations of an electronic design may include using a processor, automatically selecting a plurality of cutpoints in the two representations of the electronic design; using a processor, automatically executing a prove-from strategy on the plurality of cut point pairs to identify a failed cut point pair in the two electronic designs; and using the processor, automatically extending a trace corresponding to the identified failed cut point pair to identify a deeper failed cut point pair or a failed output pair in the two electronic designs.

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Karmiel, Israel

Ayman Hanna