Motorola Corporation

Arizona State University

Radiusai, Inc.

Aykut Dengi

Sarma Vrudhula

Edward Outlaw Travis, Jr

Ruiqi Tian

Niranjan Kulkarni

Tat-Kwan Edgar Yu

Sejal N Chheda

Mark S Roberton

James W Miller

Michael G Khazhinsky

Alfred J Reich

Abhinav Yarlagadda

Robert Elliott Boone

Jinghua Yang

Thomas Adam Strich

Sri Priyanka Madduluri

Kamalesh Kalirathinam

Rahul Santhosh Kumar Varma

Sai Krishna Bashetty

Daniel King

Nathan Kelly

Joseph Davis

Assisted checkout devices, including point-of-sale stations, can use computer vision and machine learning to speed the checkout process while maintaining human verification, assistance, and customer interaction provided by human clerks. A plurality of optical sensors, including cameras, can be arranged with different views of a checkout plane upon which items being purchased by a buyer are placed. Moreover, one or more support towers can be utilized to elevate the optical sensors to vertical heights at which the checkout plane, and items placed thereon, is within the field of view of the optical sensors. The information captured by the plurality of optical sensors can be analyzed using machine learning models to detect and identify the items placed on the checkout plane.

Point of sale station for assisted checkout system

A non-volatile logic device for energy-efficient logic state restoration is disclosed. The non-volatile logic device incorporates a volatile flip-flop and a non-volatile storage unit to achieve on-chip non-volatile storage. The non-volatile logic device further allows for a backup time to be determined on a per-chip basis, resulting in minimizing energy wastage and satisfying a given yield constraint.

Non-volatile logic device for energy-efficient logic state restoration

This disclosure relates generally to digital synchronous circuits that introduce clock skew without requiring clock buffers in a clock network. In one embodiment, the digital synchronous circuit includes a first flip flop and a second flip flop. The first flip flop is synchronized to be transparent and to be opaque in accordance with a first clock signal while the second flip flop is configured such that the second flip flop is synchronized to be transparent and to be opaque in accordance with a second clock signal. However, the second flip flop is configured to generate the first clock signal such that the second flip flop provides the first clock signal in a first clock state in response the second flip flop becoming transparent and provides the first clock signal in a second clock state in response the second flip flop becoming opaque thereby providing a clock skew without clock buffers.

Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital VLSI designs

A threshold logic element (TLE) is disclosed. The TLE includes a first input gate network, a second input gate network, and a differential sense amplifier. The first input gate network is configured to receive a first set of logical signals and the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. To obfuscate the TLE, any number of obfuscated transmission gates can be provided in one or both of the input gate networks. The obfuscated transmission gates are obfuscated such that obfuscated transmission gates are incapable of effecting the threshold logic function of the TLE and thus hide the functionality of the TLE.

Method of obfuscating digital logic circuits using threshold voltage

Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).

Method for adding features to a design layout and process for designing a mask

A number of small wells under the isolation layer are formed using the same mask made of photoresist and implant step that is used for the regular wells. The small wells are formed close enough together so that they merge during normal subsequent semiconductor processing to form a merged well. The normal wells and the small wells have a concentration that is greater than that of the merged well. The desired merging of the small wells is ensured by making sure that the small wells are sufficiently close together that the normal diffusion of well implants, which occurs from the particular semiconductor process that is being used, results in the merging. One desirable use of the merged well, with its lower doping concentration, is as a resistor that has more resistance than that of the regular well without requiring an additional implant.

Method for forming a well under isolation and structure thereof

Semiconductor device and a process for designing a mask

Growing community of inventors

Tempe, AZ, United States of America

Aykut Dengi