Qualcomm Incorporated

Ayan Paul

Po-Hung Chen

David Li

Derek Yang

Chulmin Jung

Sung Son

Rahul Biradar

Biju Manakkam Veetil

Shivendra Kushwaha

Ravindra Reddy Chekkera

Xiao Chen

Chen-ju Hsieh

Chun-Yen Lin

A memory is provided with a pseudo-differential sense amplifier for single-endedly sensing a first read bit line from a first bank of bitcells. The sense amplifier compares a voltage of the first read bit line to a voltage of a pre-charged second read bit line from a second bank of bitcells to make a bit decision for a read operation through the first read bit line to the first bank of bitcells.

Pseudo-differential de-glitch sense amplifier

A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Memory circuit architecture

Various implementations provide systems and methods for writing data to memory bit cells. An example implementation includes a write circuit that couples both a bitline and a complementary bitline to power (VDD) by positive-channel metal oxide semiconductor (PMOS) transistors. By using PMOS transistors instead of NMOS transistors at the applicable nodes, such implementations may avoid a voltage drop between VDD and the bitlines, thereby allowing the bitlines to reach a substantially full VDD voltage level when appropriate. Additionally, various implementations avoid dynamic nodes that share charge across NMOS transistors, thereby allowing a given bitline to reach a substantially full VDD voltage level when appropriate. Accordingly, some implementations may experience higher levels of writability and static noise margin than other implementations.

Memory write methods and circuits

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Ayan Paul