Qualcomm Incorporated

Ayala Miller

Amit Gil

Shaul Yohai Yifrach

Tomer Rafael Ben-Chen

Dan Gilboa Waizman

Deepak Jindal

Hardware-based packet processing circuitry is provided. In this regard, hardware-based packet processing circuitry includes header processing circuitry and payload processing circuitry. The hardware-based packet processing circuitry receives a header portion and a payload portion of an incoming packet in a first packet format. The header processing circuitry and the payload processing circuitry process the header portion and the payload portion to form a processed header portion and a processed payload portion, respectively. The hardware-based packet processing circuitry generates an outgoing packet in a second packet format based on the processed header portion and the processed payload portion. By processing the incoming packet separately in the header processing circuitry and the payload processing circuitry, it is possible to accelerate selected steps (e.g., ciphering/deciphering, compression/de-compression, checksum, etc.) of packet processing via dedicated hardware functional block(s), thus reducing computing resource requirement and overhead associated with software-based packet processing.

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Haifa, Israel

Ayala Miller