Intel Corporation

Mellanox Technologies, Ltd.

Apple Inc.

Ayal Eshkoli

Igal Kushnir

Shahar Porat

Ofir Degani

Rotem Banin

Eng Hun Ooi

Elan Banin

Eytan Mann

Amir Israel Rubin

Ran Shimon

Yossi Tsfati

Ronen Gernizky

Elinor Kashani

Dmitry Felsenstein

Vladimir Volokitin

Stefan Meyer

Tal Davidson

Eshel Gordon

Johannes Brendel

Sharon Malevsky

Roi Levi

Boris Sharav

Tomer Gidoni

Tom Romano

Tai Davidson

Amir Rubin

Technologies for chip-to-chip (C2C) yield and performance optimization in a die stacking platform are described. One apparatus includes a substrate, a first integrated circuit disposed on the substrate at a first location, a second integrated circuit disposed on the substrate at a second location, and a third integrated circuit disposed on the second integrated circuit. The second integrated circuit is coupled to the first integrated circuit using a first chip-to-chip (C2C) interface via a physical terminal. The third integrated circuit is coupled to the first integrated circuit using a second C2C interface via the physical terminal. Only one of the first C2C interface and the second C2C interface is active at a time.

C2C yield and performance optimization in a die stacking platform

A digital-to-charge converter, a digital-to-analog converter, and a method of operating a digital-to-charge converter are provided. An illustrative method of operating a digital-to-charge converter is provided that includes: receiving a digital input signal at the digital to charge converter, charging one or more capacitors during a pre-evaluation period, where the one or more capacitors are charged with a supply voltage based the digital input signal, disconnecting the one or more capacitors from the supply voltage during an evaluation period, and generating an analog output signal from the digital to charge converter based on an evaluation of charge of the one or more capacitors during the evaluation period.

High speed charge mode digital-to-analog converter

An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

Time encoded data communication protocol, apparatus and method for generating and receiving a data signal

Methods, systems, and circuitries are provided to generate clock signals of different qualities in a device. A method includes determining whether the device is operating in a mid power mode or a high power mode. In response to determining that the device is operating in the mid power mode, oscillator circuitry is controlled to cause the oscillator circuitry to consume a lower amount of power, such that the oscillator circuitry generates a lower quality clock signal. In response to determining that the device is operating in the high power mode, the oscillator circuitry is controlled to cause the oscillator circuitry to consume a higher amount of power, such that the oscillator circuitry generates a higher quality clock signal. The lower amount of power and the higher amount of power are different from one another.

Mid power mode for an oscillator

Growing community of inventors

Kiryat Tivon, Israel

Ayal Eshkoli