Kabushiki Kaisha Toshiba

Ayako Yamano

Hitoshi Shiga

Osamu Nagao

Koichi Fukuda

Toshiaki Edahiro

Teruo Takagiwa

Norihiro Fujita

A nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array comprises a plurality of memory cells and stores initial setting data in the plurality of memory cells. The control circuit is configured to apply a first voltage to gates of the plurality of memory cells to read the initial setting data and, depending on that read result, apply a second voltage different from the first voltage to the gates of the plurality of memory cells to read the initial setting data.

Nonvolatile semiconductor memory device and read method thereof

According to one embodiment, a semiconductor memory device includes a plurality of blocks in a memory cell, each of the blocks acting as an erasure unit of data, the block including a plurality of pages, each of the pages including a plurality of memory cell transistors, each of the memory cell transistors being configured to be an erasure state or a first retention state based on a threshold voltage of the memory cell transistor, and a controller searching data in the block with respect to, writing a first flag denoting effective into a prescribed page of the block with the erasure state, and writing the first flag denoting non-effective into a prescribed page of the block with the first retention state, reading out the prescribed page of the block with the first retention state, and determining that the block is writable when the first flag denotes effective.

Semiconductor memory device and method for writing therein

A nonvolatile semiconductor storage device according to an embodiment includes an erase circuit executing an erase sequence, wherein in the erase sequence, the erase circuit executes: an erase operation to change a selection memory cell group to an erased state, after the erase operation, a soft program operation on the selection memory cell group to solve over-erased state, and after the soft program operation, a first soft program verification operation performed on at least one partial selection memory cell group of a first partial selection memory cell group and a second partial selection memory cell group so as to confirm whether the partial selection memory cell group includes a predetermined number of memory cells or more that have threshold values equal to or more than a predetermined first threshold value, and after the first soft program verification operation.

Growing community of inventors

Yokohama, Japan

Ayako Yamano