Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Ajinomoto Co., Ltd.

Ayako Sato

Shinnosuke Kamata

Toshiya Uchida

Masato Matsumiya

Tatsuya Kanda

Tatsushi Otsuka

Tetsuo Miyamoto

Hidenaga Takahashi

Yoshinobu Yamamoto

Masanori Kurita

Satoru Shirakawa

Satoshi Eto

Takahiko Sato

Hiroyuki Kobayashi

Hitoshi Ikeda

Takaaki Suzuki

Masafumi Yamazaki

Toshikazu Nakamura

Toshiya Miyo

Yasurou Matsuzaki

Kenichi Kawasaki

Tomohiro Kawakubo

Noriko Kawamura

Syusaku Yamaguchi

Takayuki Ito

Masayuki Sugiki

Natalia Viktorovna Stoynova

Sergey Vasilievich Smirnov

Takayuki Yoneda

Tatsuki Kashiwagi

Uno Tagami

Elena Viktorovna Sycheva

Eri Higashiura

Misato Okamoto

Erika Watanabe

Yuki Oda

Elena V Matrosova

Natalia V Geraskina

A mutant glutathione synthetase (GSHB) suitable for generating &#x3b3;-Glu-Val-Gly, and a method for producing &#x3b3;-Glu-Val-Gly using the same are provided. &#x3b3;-Glu-Val-Gly is produced by using a mutant GSHB having a mutation at such a position as V7, N13, I14, N15, K17, F22, F95, M165, N199, Y200, P202, I274, T285, and P287.

Mutant glutathione synthetase and method for producing gamma-glutamyl-valyl-glycine

A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

Multi-port memory based on DRAM core

Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

Memory device, memory controller and memory system

An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

A twin-cell type semiconductor memory device in which the area of a chip can be reduced. In the twin-cell type semiconductor memory device for storing data in at least one pair of memory cells as complementary information, memory cells are arranged at each of a plurality of word lines at intervals at which bit lines are located. At least the one pair of memory cells, which have stored the complementary information and which indicate a plurality of areas each connected to a pair of bit lines, form a twin cell.

Semiconductor memory device for storing data in memory cells as complementary information

An external terminal receives an external signal so as to access the first and second memory chips. The test starting terminal receives a test starting signal activated when the first or second memory chip is tested and inactivated when the first and second memory chips are normally operated. The access signal generator converts the external signal to a memory access signal of the first memory chip. The first selector selects the external signal, which is a test signal, during activation of the test starting signal, selects the memory access signal during the inactivation of the test starting signal. That is, during the test modes, the first memory chip can be directly accessed from the exterior. For this reason, the test program for testing the first memory chip alone can be diverted as the test program following an assembly of the semiconductor device.

Semiconductor device

A semiconductor memory device includes a memory core circuit, a command circuit which receives commands from an exterior of the device at intervals at least as long as a minimum command cycle, a timing generator configured to request a read access to the memory core circuit immediately after inputting of a read command if a command supplied from the exterior to the command circuit is the read command, to perform a read operation on the memory core circuit immediately after the request of the read access if there is no currently performed operation in the memory core circuit, to request a write access to the memory core circuit after data is fixed prior to an end of a command cycle during which a write command corresponding to the write access is entered from the exterior to the command circuit, to perform a write operation on the memory core circuit immediately after the request of the write access if there is no currently performed operation in the memory core circuit, and to control an order of a plurality of accesses if the plurality of accesses conflict with each other with regard to access to the memory core circuit.

DRAM having SRAM equivalent interface

Growing community of inventors

Kawasaki, Japan

Ayako Sato