Fujitsu Corporation

Fujitsu Microelectronics Limited

Ayako Kitamoto

Masato Matsumiya

Masato Takita

Satoshi Eto

Toshikazu Nakamura

Kuninori Kawabata

Toru Koga

Hideki Kanou

Yuki Ishii

Masatomo Hasegawa

Kaoru Mori

Shinichi Yamada

Mitsuhiro Higashiho

Hideki Kano

Koichi Nishimura

Masao Taguchi

Yoshinori Okajima

Atsushi Hatakeyama

Akira Kikutake

Shusaku Yamaguchi

Yuichi Uzawa

A semiconductor device, including a word line driver for driving a word line connected to a memory cell in a memory cell array and for resetting the word line when the memory cell changes from an activated to a standby state. The reset level of the word line driver is set when resetting of the word line is performed, and may be switched between first and second potentials. A word line reset level generating circuit varies the amount of negative potential current supply in accordance with memory cell array operating conditions. The semiconductor device includes a plurality of power source circuits, each having an oscillation circuit and a capacitor, for driving the capacitor via an oscillation signal outputted by the oscillation circuit. At least some power source circuits share a common oscillation circuit, and different capacitors are driven via the common oscillation signal.

Semiconductor memory device capable of driving non-selected word lines to a variable negative potential based on a bank access operation

A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

Semiconductor device

A semiconductor device includes a word line drive circuit resetting the word line by driving the word line connected to a memory cell and switching a reset level of the word line drive circuit at the time of the reset operation of the word line. Further, a semiconductor device includes a memory cell array formed by arranging a plurality of memory cells and a reset level switch circuit for selecting a first potential or a second potential and supplying the first potential or the second potential to the word line drive circuit.

Semiconductor memory device capable of driving non-selected word lines to first and second potentials

Transistors are supplied with either a first power supply voltage or a second power supply voltage lower than the first power supply voltage. During an operation period of the transistors, substrate voltages of the transistors are set at a value between the first power supply voltage and the second power supply voltage. The substrate voltages are changed to lower threshold voltages of the transistors so that the transistors improve in drivability and operating speed. Therefore, neither a booster for generating higher voltages nor a pumping circuit for generating negative voltages is particularly required. This allows a reduction in layout size. Besides, in accordance with the operating state of the semiconductor integrated circuit, the transistor characteristics can be easily changed by changing the threshold voltages of the transistors.

Substrate voltage selection circuit

The present invention is that, in a memory circuit comprising a cell array and peripheral circuit, the cell array power source is supplied to a circuit which operates during the power-down mode in addition to the cell array. The circuit which operates during the power-down mode is, for example, a self-refresh circuit. A dynamic memory requires refreshing operations in fixed intervals even during the power-down mode. Therefore, the self-refresh circuit is operating even during the power-down mode. Thus, by supplying the cell array power source to the self-refresh circuit, it is possible to consume a prescribed quantity of current from the cell array power source generation circuit to an extent of being able to maintain the level thereof even during the power-down mode. The cell array power source may be maintained within an appropriate voltage range thereby.

Memory circuit for preventing rise of cell array power source

A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.

Semiconductor integrated circuit and method of switching source potential of transistor in semiconductor integrated circuit

A semiconductor memory device includes bit lines which transfer data of memory cells, a sense amplifier which is connected to the bit lines, and amplifies data on the bit lines that appears in response to an external access, and a latch circuit which is connected to the bit lines, and amplifies and latches data on the bit lines that appears as data to be refreshed.

Semiconductor memory device with concurrent refresh and data access operation

A semiconductor memory device includes a DQ-quantity-selection signal generation circuit which generates a DQ-quantity-selection signal indicative of a number of input/output data bits, bit lines which transfer read data and write data for memory cells, and a plurality of sense amplifiers which are connected to the bit lines, and are activated as many as indicated by the DQ-quantity-selection signal.

Semiconductor memory device with reduced current consumption

During a read operation, data read from memory cells onto bit lines are amplified simultaneously by sense amplifiers and outputted to the exterior of a memory. In this operation, a data control circuit outputs to the exterior all the data read from the memory cells onto the bit lines and amplified simultaneously by the sense amplifiers. During a write operation, data supplied from the exterior to the bit lines are amplified by the sense amplifiers and written into the memory cells. In this operation, the data control circuit writes into the memory cells all the data inputted from the exterior and amplified simultaneously by the sense amplifiers. Since all the data amplified simultaneously by the sense amplifiers are inputted/outputted from/to the exterior, the data transfer rate of the input/output data can be improved and the power consumption per unit amount of transferred data can be reduced.

Semiconductor memory having a wide bus-bandwidth for input/output data

A semiconductor memory device includes a core area formed of memory blocks each having a relaxed sense amplifier arrangement, a data bus including data bus lines corresponding to the memory blocks, a plurality of input/output terminals provided in number corresponding to the data bus lines forming the data bus, and a data path switch circuit provided between the data bus the input/output terminals for providing interconnection paths between the input/output terminals and the data bus lines, wherein the data path switch circuit switches a part of the interconnection paths in response to a switch control signal such that the input/output terminals are connected respectively to predetermined memory cells located at respective, predetermined physical locations in any of the memory blocks.

Semiconductor memory device having a relaxed pitch for sense amplifiers

In the semiconductor memory, a refresh signal is generated and the refresh operation is performed based on the refresh signal. Parity is generated when data is written and the generated parity is stored. When the refresh operation and a usual data read or write operation overlap, data in a memory cell which cannot be read because the refresh operation is given priority is determined based on the parity. Data which cannot be written because the refresh operation is given priority is held temporarily in a write data buffer. When the refresh operation is not overlapped for the usual data read or write operation, the data held in the write data buffer is rewritten in a corresponding memory cell.

Semiconductor memory, and memory access method

A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.

Variable delay circuit and semiconductor integrated circuit device

To reduce current consumption, there is provided a circuit for each bank, comprising selection circuits,through,each for selecting either a normal supply voltage Vii or a higher supply voltage Vjj as a supply voltage VH,in response to a selection control signals SC,and *SC,a selection control circuit,for generating the signals SC,and *SC0 to make the selection circuits select Vii when a bank activation signal BRAS,is inactive and Vjj for a predetermined period in response to activation of BRAS,and sense amplifier driving circuits,through,for supplying the ground voltage and VH,to the sense amplifier rows in response to activation of sense amplifier control signals. To stabilize the output voltage Vii of the power supply circuit having a NMOS transistor, the drain electrode, gate and source electrodes of which are at VCC, VG and approximately Vii&equals;VG&minus;Vth, where Vth is the threshold voltage of the NMOS transistor,a leak circuit is employed. The leak circuit has a NMOS transistor connected between Vii and ground. Wasteful power consumption by the current flowing to the leak circuit is negligibly small, e.g. 1 to 10 &mgr;A, and the variation of the supply voltage Vii reduces effectively.

Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type

According to a semiconductor memory for one aspect of the present invention, a memory cell transistor is formed in a P-type first well region which is formed at the surface of a P-type semiconductor substrate, and a back bias voltage is applied to the P-type first well region and the P-type substrate. Further, an N-type retrograde region is formed by implanting a high energy N-type impurity, so that a deeper, N-type second well region is formed by employing the N-type retrograde region. Further, a P-type third well region is formed in the N-type second well region, and a P-type emitter region is also formed therein. Thus, together the P-type emitter region, the N-type second well region, and the P-type third well region constitute a lateral PNP transistor. In addition, the ground voltage is maintained for the P-type third well region, which serves as a collector region.

Semiconductor memory device

A transistor of a driver in the semiconductor integrated circuit according to the present invention has its gate connected to a controlling circuit, and has its drain connected to a sense amplifier. The controlling circuit supplies the gate of the transistor with a gate-to-source voltage exceeding or below other power supply voltages. The drain-to-source resistance of the transistor in the on state becomes sufficiently lower as compared with that in the case of supplying the power supply voltages between the gate and source of the transistor. Accordingly, the amplifying speed of the sense amplifier is heightened without altering the sense amplifier and the driver. Besides, the amplifying speed of the sense amplifier is heightened without raising the power supply voltage which supplies the carriers to the driver. The semiconductor memory device according to the present invention switches the driving supply voltage for the sense amplifier from the first supply voltage, to the second supply voltage lower than the first voltage. The timing at which the first supply voltage is switched to the second supply voltage is controlled in accordance with the voltage on a dummy bit line which is driven by a monitoring sense amplifier. Accordingly, even when the driving speed of the sense amplifier using the overdriving system has fluctuated due to the fluctuation of the first supply voltage, the driving supply voltage of the sense amplifier can be always switched to the second supply voltage at the appropriate timing.

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Kawasaki, Japan

Ayako Kitamoto