Kabushiki Kaisha Toshiba

Ayako Hirata

Kazuhiko Kasai

Tadahiro Kuroda

Kenji Matsuo

Shinji Fujii

Masahiro Kimura

Toshiyuki Fukunaga

Kiyoshi Mukaine

An input buffer circuit includes an output circuit and supplies a plurality of signals in response to an input signal. A delay line is constituted of a plurality of delay cells connected in series and delays the signals supplied from the input buffer circuit. A PLL circuit connected to the delay line, includes a level converter which outputs a control signal for controlling a delay time of the delay line. An output signal generation circuit generates a signal having a multiplied frequency from the output signal of the input buffer circuit and the output signal of a tap of the delay line. Each of the delay cells has an output circuit having the same arrangement as that of the output circuit provided in the input buffer circuit, and a clocked inverter circuit included in each of the output circuits of the delay cells and input buffer circuit is controlled by the control signal output from the level converter. Therefore, the waveform of the signal output from the output circuit of the input buffer circuit can be made identical with that of the signal output from the output circuit of each delay cell, and the signal having the multiplied frequency output from the output signal generation circuit has a fixed duty ratio.

Frequency multiplier circuit

The gate of a first P-channel transistor of a first comparator is supplied with an input signal, and the gate of a second P-channel transistor of the first comparator is supplied with a reference voltage. An output terminal of the first comparator is connected to an output circuit and the gates of first and second P-channel transistors of a second comparator are supplied with the reference voltage. The second comparator outputs a voltage equal to a stand-by time output voltage of the first comparator and the output voltage from the second comparator is supplied to the non-inversion input terminal of a third comparator which is connected to a voltage generating circuit. The voltage generating circuit has substantially the same dimension ratio as the output circuit and generates a voltage equal to the threshold voltage of the output circuit. A third comparator controls the first P-channel transistors of the first and second comparators in accordance with a difference voltage between the output voltage of the second comparator and the output voltage of the voltage generating circuit to thereby automatically set a stand-by time output voltage of the first comparator at a value close to the threshold of the output circuit.

Semiconductor integrated circuit capable of compensating errors in

Growing community of inventors

Chigasaki, Japan

Ayako Hirata