Semiconductor Energy Laboratory Co., Ltd.

Aya Miyazaki

Hiroyuki Miyake

Mitsuaki Osame

Shunpei Yamazaki

Koji Kusunoki

Kouhei Toyotaka

Hideaki Shishido

Seiko Amano

Ryo Arasawa

Shigeharu Monoe

Satoshi Seo

Masayuki Sakakura

Yoshifumi Tanada

Keisuke Miyagawa

An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.

Pulse signal output circuit and shift register

It is an object of the present invention to provide a display device where power consumption can be suppressed and the number of gray scales can be increased without a scanning line driver circuit on both sides of a pixel portion. In a display device having a scanning line driver circuit, a shift register included in the scanning line driver circuit has 4m-stage (m is a natural number) flip-flop circuits in every m scanning lines, and a signal which selects the scanning line in a first half period of one scanning line selection period and a signal which selects the scanning line in a second half period of the one scanning line selection period are output to the scanning line by another start pulse.

Display device and electoric device having the same

If the frequency of a clock signal is increased, the pulse width of a sampling pulse is decreased, and the amount of time for a video signal to be written to a source line is inadequate. Sampling pulses (sam) rise sequentially in synchronization with the rise of a start pulse (SP). As the start pulse (SP) rises, synchronized with the rise of clock signals (CK, CKB), the sampling pulses (sam) fall off sequentially, delayed by half the period of the clock signals (CK, CKB) for every step. As a result, the sampling pulses (sam) with a pulse width longer than one period of the clock signals (CK, CKB) are generated. In a period T, a desired video signal (VIDEO) is written to its corresponding source line. In this way, the time for half a period of the clock signal can be secured for writing to the source line.

Source line driving circuit, active matrix type display device and method for driving the same

A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, a source and drain regions, a floating gate, and a control gate. Each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region.

Semiconductor device

An object is to provide a semiconductor device in which damages of an element such as a transistor are reduced even when physical force such as bending is externally applied to generate stress in the semiconductor device. A semiconductor device includes a semiconductor film including a channel formation region and an impurity region, which is provided over a substrate, a first conductive film provided over the channel formation region with a gate insulating film interposed therebetween, a first interlayer insulating film provided to cover the first conductive film, a second conductive film provided over the first interlayer insulating film so as to overlap with at least part of the impurity region, a second interlayer insulating film provided over the second conductive film, and a third conductive film provided over the second interlayer insulating film so as to be electrically connected to the impurity region through an opening.

To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.

Method for deleting data from NAND type nonvolatile memory

The present invention provides nonvolatile semiconductor memory devices which operate with low power consumption. In a nonvolatile semiconductor memory device, a plurality of nonvolatile memory elements are connected in series. The plurality of nonvolatile memory elements include a semiconductor layer including a channel forming region and a control gate provided to overlap with the channel forming region. Operations of write, erase, a first read, and a second read in a verify operation of data to the nonvolatile memory elements, are conducted by changing voltage to the control gates of the nonvolatile memory elements. The second read in the verify operation after erase operation is conducted by changing only one of a potential of the control gate of a nonvolatile memory element which are selected from the plurality of nonvolatile memory elements, and as the potential, a potential different from a potential of the first read is used.

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Kanagawa, Japan

Aya Miyazaki