Mindspeed Technologies, Inc.

Infineon Technologies North America Corp.

Parimics, Inc.

Infineon Technologies Ag

Axel K Kloth

Daniel Fu

Paul Bergantino

Moshe De-Leon

Warner Andrews

Stephen M Mills

Jeremy Bicknell

An image processing system includes, in part, an image processing engine adapted to perform object-independent processing corresponding to a first processing layer of the image processing system, a post processing engine adapted to perform object-dependent processing corresponding to a second processing layer of the image processing system, and a processing engine adapted to perform object composition, recognition and association corresponding to a third processing layer of the image processing system. The image processing engine includes a multitude of processors each associated with a different one of the pixels of the image. The post processing engine includes an N-way symmetric multi-processing system (SMP) having disposed therein N DFT engines and N matrix multiplication engines, where N is an integer greater than 1. The multitude of the processors of the image processing engine are formed on a semiconductor substrate different from the semiconductor substrate on which images are captured.

Method and apparatus for image processing

An image processing system processes images via a first processing layer adapted to perform object-independent processing, a second processing layer adapted to perform object-dependent processing, and a third processing layer adapted to perform object composition, recognition and association. The image processing system performs object-independent processing using a plurality of processors each of which is associated with a different one of the pixels of the image. The image processing system performs object-independent processing using a symmetric multi-processor. The plurality of processors may form a massively parallel processor of a systolic array type and configured as a single-instruction multiple-data system. Each of the plurality of the processors is further configured to perform object-independent processing using a unified and symmetric processing of N dimensions in space and one dimension in time. The plurality of processors are formed on a semiconductor substrate different from the semiconductor substrate on which images are captured.

A method and apparatus is disclosed for interfacing an asynchronous network with a synchronous network and in particular for efficiently utilizing available bandwidth of a synchronous network transmit opportunity. In one embodiment asynchronous traffic arrives via an asynchronous network at a network device, such as a switch, for transmission over a synchronous network. The traffic is parsed into cells and after switching, a reassembly unit is provided for processing one or more cells buckets. Write operations occur based on an ingress pointer while read operations are controlled by an egress pointer. Upon occurrence of a transmit opportunity on the synchronous network, the entire bandwidth of the transmit opportunity is utilized by loading awaiting cells from bucket memory on to the synchronous network. Sufficient cells are stored in memory between the memory locations identified by the ingress pointer and the egress pointer to insure total utilization of transmit opportunity bandwidth.

Pseudo synchronous machine

System and method for dynamically altering bandwidth allocation to each region serviced by a network. Each region is allocated an initial estimated bandwidth on the network and compares instantaneous demand against the allocation. When demand falls below the allocation, the region releases bandwidth so other regions can take advantage of that bandwidth. When demand exceeds the allocation, the region takes advantage of bandwidth released by other regions.

Dynamic bandwidth allocation for wide area networks

A router () includes one or more input ports () and one or more output ports (). The router () includes a lookup table () to determine routing of the incoming packets or cells. The lookup table is implemented in dynamic random access memory (DRAM) with a portion implemented as static random access memory (SRAM) (). The SRAM () is used to store a first search level of destination addresses. Once the first search level in SRAM () has been exhausted, the search moves to the DRAM portion ().

SRAM based cache for DRAM routing table lookups

Method and apparatus for lossless switchover in a redundant switch fabric improves the reliability and predictability of a cell reaching its destination without the cell being lost during switch-over through redundant switch fabrics. Ingress and egress buffers are disposed in input and output line cards to maintain the history of transmitted cells. When switch-over occurs, the cells transmission history is used to recover lost cells transparently and with minimal latency.

Method and apparatus for lossless switchover in a redundant switch fabric

A apparatus and method that provides a routing engine for processing data packets based upon certain rules that are compiled and applied real-time via a just-in-time (JIT) compiler, a runtime compiler, or the like. The routing engine parses and analyzes an incoming IP flow. A set of rules are developed and stored for use by the JIT. The rules establish a set of patterns, and the incoming data is compared to those patterns. If certain patterns are detected, then the associated action established by the rule is applied to the processing of the data packet. Packets are classified according to any rule, as applied to any packet, as early as possible in the process (i.e. first or second stage of process), with the route lookup and packet attribute processes performed in parallel. Data packets might be assigned or mapped to various traffic service levels. Traffic types and priorities, as well as service levels, can be mapped onto existing QoS/CoS definitions and assignments. The data packets can be altered or modified as a result of the detected patterns. Data packets can also be discarded or dropped if the detected patterns and associated rule indicate such a desire. The apparatus and method might be implemented as a hardware and software configuration. A software configuration might also be loaded into existing router hardware.

Rule based IP data processing

Access control to protected resources in a multiprocessor system is implemented without additional use of the processor bus. A bridge interconnects each processor with shared resources. The bridge has a semaphore corresponding to each protected resource indicating if the corresponding resource is available. The bridge halts a processor requesting access to any resource having a corresponding semaphore indicating the requested resource is not available.

Semaphore access in a multiprocessor system

An optical fiber interconnect is provided having a tetrahedral or corner cube retroreflector. The optical fibers are provided in sufficiently close proximity to the retroreflector that a desired level of reflected light is provided to the receiving fiber. In one embodiment, the optical fibers are provided in contact with the retroreflector.

Growing community of inventors

Mountain View, CA, United States of America

Axel K Kloth