Koninklijke Philips Corporation N.v.

St-ericsson Sa

Nxp B.v.

Axel Hertwig

Harald Bauer

Urs Fawer

Stefan Marco Koch

Hans-Joachim Gelke

Paul Lippens

Cornelis Hermanus Van Berkel

Frank Heinle

Patrick Peter Elizabeth Meuwissen

Stephan Koch

Rainer Mehling

A multiprocessor system, more particularly for terminal devices of mobile radiotelephony, in which system are arranged on a common chip:

Memory sharing arrangement for an integrated multiprocessor system

To achieve a shortening of the initial synchronization time and/or extension of the stand-by time with a method of connecting an UMTS mobile radio to a network, the UMTS mobile radio receives and stored in one or more time-limited RF receive windows the signals that are subsequently evaluated when the HF receiver is switched off.

Method of connecting an UMTS mobile radio to a network

A system () comprising at least two integrated processors (Pand P). These two processors (Pand P) are operably connected via a communication channel () for exchanging information. One processor (P) has a processor bus (), a shareable unit (), and a DMA unit () with an external DMA channel (). The DMA unit () and the sharable unit () are connected to the processor bus (). The other processor (P) has an access unit () which is a connectable to the external DMA channel () of the DMA unit (). Due to this arrangement, a communication channel () can be established from the access unit () which is connectable to the external DMA channel (), the DMA unit (), and the processor bus ().

Inter-processor communication system for communication between processors

A multiprocessor array with a first shadow register unit () which operates within a first clock domain, at least one second shadow register unit () which operates within a second clock domain, and a peripheral unit () which operates within a peripheral clock domain. Within all clock domains there are provided register units () which have a construction that is functionally identical.

Multiprocessor array

Processor memory system

A method of operating a storage system comprising a main memory and a cache memory structured in address-related lines, in which cache memory can be loaded with data from the main memory and be read out by a processor as required. During the processor's access to data of a certain address in the cache memory, at which address certain data from the main memory which has a corresponding address is stored, a test is made to determine whether sequential data s stored at the next address in the cache memory; and this sequential data, if unavailable, can be loaded from the main memory in the cache memory via a prefetch, the latter only taking place when the processor accesses a predefined line section lying in a line.

Method of operating a storage system and storage system

This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile flash memory ( ) into an IC. To integrate such a flash memory into an IC raises some problems which are solved by providing a dedicated flash bus ( ) which operationally links the flash memory ( ) with one or more microprocessors ( ) on the IC. Preferably, the flash bus ( ) controls the flash-memory-specific commands and has a width greater than, in particular a multiple of, the width of the microprocessor ( ) and/or the flash memory ( ) to compensate for the relatively slow access time of the flash memory. It is especially advantageous to structure the system as a master/slave bus system for operating the flash memory ( ) and to link the flash bus via bridges ( ) to the microprocessor/s ( ,) and through a shell ( ) to the flash memory ( ). For operating such a system, a flash bus arbiter ( ) may be necessary or advantageous.

Growing community of inventors

Nürnberg, Germany

Axel Hertwig