Infineon Technologies Ag

Nan Ya Technology Corporation

Infineon Technologies Austria Ag

Axel Buerke

Sven Schmidbauer

Ravi Keshav Joshi

Yi-Jen Lo

Michael Nelhiebel

Rainer Pelzer

Chiang-Hung Lin

A semiconductor device includes a semiconductor substrate, a power metallization structure formed above the semiconductor substrate and a barrier layer formed between the power metallization structure and the semiconductor substrate. The barrier layer is configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate. The power metallization structure is in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region. The semiconductor device further includes a passivation layer interposed between the barrier layer and the power metallization structure in a second region. Corresponding methods of manufacturing the semiconductor device are also described.

Power metallization structure for semiconductor devices

A method for controlling a thickness of a first layer of an electrical contact of a semiconductor device, whereby the semiconductor device comprises a semiconductor layer, a first layer and a second layer, whereby at least a part of the semi-conductor layer is covered with the first layer, whereby at least a part of the first layer is covered with the second layer, whereby the second layer is exposed to a plasma gas, whereby an upper face of the first layer adjacent to the second layer is treated by the plasma gas and an interlayer is generated between the first and the second layer reducing the thickness of the first layer.

Method for controlling a thickness of a first layer and method for adjusting the thickness of different first layers

Growing community of inventors

Dresden, Germany

Axel Buerke