Cypress Semiconductor Corporation

Avri Harush

Kobi Danon

Amir Rochman

A time-to-digital converter (TDC) circuit includes phase error calculation circuitry to: determine phase error values based on a time difference between a input reference clock and a feedback clock of a digital phase-locked loop (DPLL) circuit, the input reference clock and the feedback clock being unsynchronized; and provide the phase error values to a digital loop filter (DLF) of the DPLL circuit. The TDC circuit further includes clock generation circuitry to: generate a filter clock that asserts a clock pulse in response to detecting each last-received pulse of the input reference clock and the feedback clock; and provide the filter clock to the DLF concurrently with providing the phase error values to the DLF that are synchronized to the filter clock.

Independently clocking digital loop filter by time-to-digital converter in digital phase-locked loop

A digitally-controlled oscillator (DCO) circuit includes a digital-to-analog converter (DAC) to generate a first current based on most significant bits of a multi-bit code received from a time-to-digital converter (TDC) of a digital phase-locked loop (PLL). The DCO circuit further includes a sigma-delta modulator (SDM) to modulate least significant bits of the multi-bit code into a set of digital bits based on a first frequency of a feedback clock of the DPLL. The set of digital bits is to cause the DAC to generate a second current. The DCO circuit further includes a ring oscillator coupled to the DAC, the ring oscillator to generate an alternating-current (AC) output signal having a second frequency corresponding to a combination of the first current and the second current.

Sigma-delta modulator for high-resolution control of ring oscillator in digital phase-locked loop

A digital phase-locked loop (DPLL) includes a time-to-digital converter (TDC) to generate a multi-bit code based on a phase error between a reference clock and a feedback clock, a digital loop filter (DLF) coupled to the TDC, a digitally-controlled oscillator (DCO) circuit coupled to the DLF and to generate an output signal that is convertible to the feedback clock, and a logic component coupled to an input of the DCO circuit. The logic component is to: trigger, in response to detecting a power on of the DPLL circuit, a switch to decouple the DLF from the DCO circuit; determine, from the reference clock, a target frequency; measure a frequency of the feedback clock; and iteratively generate, based on the frequency during each iteration, a set of digital bits to the input of the DCO circuit that successively causes the frequency to converge towards the target frequency.

Faster phase-locked loop locking using successive approximation toward a target frequency

Disclosed are methods for reading a set of bits from a NVM array (such as a SPI or parallel NOR NVM or otherwise) including: retrieving each of the set of bits from the NVM array substantially in parallel, applying substantially in parallel to each of the retrieved bits a segmented search, each search indexed using an order number of the respective bit being checked, and correcting a bit whose search indicates an error.

Methods, circuits, systems and computer executable instruction sets for providing error correction of stored data and data storage devices utilizing same

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Herzeliya, Israel

Avri Harush