Spansion Israel Ltd

Saifun Semiconductors Ltd.

Infineon Technologies LLC

Avri Harush

Yoram Betser

Oleg Dadashev

Yair Sofer

Oren Shlomo

Yaal Horesh

Joseph Shor

Shai Eisen

Eran Geyari

A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global-reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.

Glitch protection system and reset scheme for secure memory devices

The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.

Pre-charge sensing scheme for non-volatile memory (NVM)

A method of reducing read disturb in NVM cells by using a first drain voltage to read the array cells and using a second, lower drain voltage, to read the reference cells. Drain voltages on global bitlines (GBLs) for both the array and the reference cells may be substantially the same as one another to maintain main path capacitance matching, while drain voltages on local bitlines (LBLs) for the reference cells may be lower than the drain voltage on local bitlines (LBLs) for the array cells to reduce second bit effect. Reducing the drain voltage of the reference cell at its drain port may be performed using a clamping device or a voltage drop device.

Minimizing read disturb in an array flash cell

According to some embodiments of the present invention, a non-volatile memory cell may be operated using a charge pump circuit. The charge pump circuit may be adapted to output a first and second voltage level, and the charge pump circuit may be connected to a first circuit segment, including a select transistor associated with the memory cell, through a switch. When the charge pump circuit is outputting power at the first voltage level, the switch may be conducting and the select transistor line may be charged. When the charge pump circuit is outputting power at the second voltage level, the switch may be opened and a second circuit segment, including a bit line associated with the memory cell, may be charged.

Method and circuit for operating a memory cell using a single charge pump

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Kyriat Bialik, Israel

Avri Harush