Freescale Semiconductor,inc.

Nxp Usa, Inc.

Avraham Dov Gal

Roi Menahem Shor

Peter Zahariev Rashev

Igor Levakov

Frederic Fernez

A predistortion method and apparatus are provided which use a DPD actuator () to apply a memory polynomial formed with first DPD coefficients to a first input signal x[n], thereby generating a first pre-distorted input signal y[n] which is provided to the non-linear electronic device () to produce the output signal, where the memory polynomial may be adaptively modified with a digital predistortion adapter () which computes second DPD coefficients u[n] with an iterative fixed-point conjugate gradient method which uses N received digital samples of the first pre-distorted input signal y[n] and a feedback signal z[n] captured from the output signal to process a set of conjugate gradient parameters (u, b, v, r, &#x3c9;, &#x3b1;, &#x3b2;) at each predetermined interval, thereby updating the first DPD coefficients with the second DPD coefficients u[n] generate a second pre-distorted input signal which is provided to the non-linear electronic device.

Fixed-point conjugate gradient digital pre-distortion (DPD) adaptation

A method is described for predistorting an input signal to compensate for non-linearities caused to the input signal in producing an output signal. The method comprises: providing an input for receiving a first input signal as a plurality of signal samples,[n], to be transmitted over a non-linear element; providing at least one digital predistortion block comprising, a plurality of IQ predistorter cells coupled to the input, each comprising a lookup table (LUT) for generating an LUT output. The at least one digital predistortion block block is configured to apply interpolation between LUT entries for the plurality of LUTs; and generate an output signal,[n], by each of the plurality of IQ predistorter cells by adaptively modifying the first input signal using interpolated LUT entries to compensate for distortion effects in the non-linear element. A combiner may be provided configured to combine the output signal samples, y, from the plurality of IQ predistorter cells into a combined signal to generate the output signal,[n], for transmission to the non-linear element. An error calculation block may be coupled to a digital predistortion adaptation block to determine and modify a predistortion performance.

Adaptive high-order nonlinear function approximation using time-domain volterra series to provide flexible high performance digital pre-distortion

A digital front end channelization device for one or more carrier signals comprises a per carrier section and a composite section. The composite section may include signal processing units, each of which may include an inverse Fourier transform unit for transforming a composite carrier signal into a time domain signal, a sample detection and selection unit for detecting and selecting a peak of the time domain signal, a clipping unit for clipping the time domain composite carrier signal to produce an error signal, a Fourier transform unit, for transforming the error signal into a frequency domain error signal, a frequency shaping unit for frequency shaping the frequency domain error signal, a summation unit for subtracting the frequency shaped frequency domain error signal from the composite carrier signal, and a phase selection unit for phase adjustment of the resulting signal.

Digital front-end channelization device

A method and apparatus are used to predistort input signal samples according to Volterra Series Approximation Model using one or more digital predistortion blocks () having a plurality of predistorter cells (-), each including an input multiplication stage (-) for combining absolute sample values received from an absolute sample delay line () into a first stage output, a lookup table () connected to be addressed by the first stage output for generating an LUT output, and a plurality of output multiplication stages (--) for combining the LUT output with samples received from the amplitude sample delay line () and signal sample delay line () to generate an output signal sample yfrom said predistorter cell, where the output signal samples yfrom the predistorter cells are combined at an output adder circuit () to generate one or more Volterra terms of a combined signal (y[n]).

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Raanana, Israel

Avraham Dov Gal