International Business Machines Corporation

Avraham Ayzenfeld

Christian Jacobi

Lee Evan Eisen

Brian William Curran

Ilya Granovsky

Emmanuel Elder

Amir Turi

Amit Shay

Giora Biran

Gregory William Alexander

Jonathan T Hsieh

Edward Thomas Malley

Eyal Naor

Yossi Shapira

Yair Fried

Richard Joseph Branciforte

Gregory Miaskovsky

Yanai Danan

Gilad Merran

Oren Ben Gigi

Omri Rafaeli

A credit-based flow control system can utilize speculative credit. If an agent has not received a credit return from a downstream agent for a given period of time, the agent can return speculative credit to an upstream agent. This way, even if the agent is not currently capable of performing operations represented by the speculative credit, the upstream agent can be enabled to proceed with operations.

Data transmission flow control regime

In an approach to processor dependency-aware instruction execution, responsive to a new instruction being issued to an instruction issue queue in a processor, a future dependency count is incremented for each instruction of a plurality of instructions in the instruction issue queue that has a dependency on the new instruction. The plurality of instructions in the instruction issue queue are prioritized based on the future dependency count. The highest priority instruction of the plurality of instructions in the instruction issue queue is issued.

Processor dependency-aware instruction execution

An example design structure tangibly embodied in a machine readable medium includes a first arithmetic logic unit (ALU) to perform fixed point instructions using at least two general registers to read data from a first and second general register of a plurality of general registers and write a result in at least a third general register of the plurality of general registers. The design structure includes a second ALU to perform non-updating fixed point instructions using at least two general registers to only read data from the general registers. The design structure includes an efficiency logic unit coupled to the first ALU and the second ALU. The efficiency logic unit is to receive an instruction and determine whether the received instruction is an updating fixed point instruction or a non-updating fixed point instruction based on a number of general registers to be used to execute the received instruction.

Microprocessor including an efficiency logic unit

Methods and systems for controlling writing to register files in a processing system having at least two execution pipelines are provided. Aspects include obtaining a micro operation for execution by an execution unit of a first pipeline in the processing system, wherein the micro operation includes writing data to a register file. Aspects also include determining whether the data will be accessed by an execution unit of a second pipeline in the processing system. Based on a determination that the data will only be accessed by the execution unit of the first pipeline, aspects include blocking writing of the data to a register file of the second pipeline.

Write power optimization for hardware employing pipe-based duplicate register files

Examples of techniques for executing instructions out of order are described herein. An example computer-implemented method includes receiving, via a processor, a plurality of instructions to be executed. The method includes sending, via the processor, an instruction to a minimal dependency queue in response to detecting the instruction includes a minimally dependent instruction. The method also includes selecting, via the processor, an instruction from a set of instructions that are eligible to be executed based on a scheme. The method further includes executing, via the processor, the instruction.

Executing processor instructions using minimal dependency queue

Examples of techniques for designing processors are described herein. In one example, a design structure can be tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure can include a logic to determine whether a received instruction is an updating fixed point instruction or a non-updating fixed point instruction. The design structure can include a first arithmetic logic unit (ALU) to execute the received instruction if the received instruction is determined to be an updating fixed point instruction and store an update value in a general register. The design structure can include a second arithmetic logic unit (ALU) to execute the received instruction if the received instruction is determined to be a non-updating fixed point instruction.

Structure for microprocessor including arithmetic logic units and an efficiency logic unit

A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises generating a functional representation of logic to determine whether an instruction is an updating instruction or a non-updating instruction. The method further comprises generating a functional representation of a first arithmetic logic unit (ALU) coupled to a general register in the processor, the first ALU to execute the instruction if the instruction is an updating instruction and store an update value in the general register, and generating a functional representation of a second ALU in the processor to execute the instruction if the instruction is a non-updating instruction.

Generating design structure for microprocessor with arithmetic logic units and an efficiency logic unit

A method, including receiving, by an extended virtual function shell positioned on a Peripheral Component Interconnect Express (PCIe) configuration space, a virtual function call comprising a request to perform a specific computation, and identifying a physical function associated with the called virtual function, the physical function one of multiple physical functions positioned on the PCIe configuration space. One or more first data values are then retrieved from a virtual function instance stored in the memory, one or more first data values, the virtual function instance associated with the called virtual function, and one or more second data values are retrieved from the identified physical function. The specific computation is then performed using the first data values and the second data values, thereby calculating a result.

Executing virtual functions using memory-based data in a PCI express SR-IOV and MR-IOV environment

An apparatus, including a first multiple of virtual function clusters positioned on a Peripheral Component Interconnect Express (PCIe) configuration space, each of the clusters comprising at least one virtual function, and a second multiple of physical functions positioned on the PCIe configuration space. The apparatus also includes an extended virtual function shell positioned on the PCIe configuration space and configured to select one of the physical functions, to select one of the available virtual function clusters and to associate the selected virtual function cluster with the selected the physical function.

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Ramat Hahayal, Israel

Avraham Ayzenfeld