Motorola Corporation

Lenslet Labs Ltd.

Avner Goren

David Galanti

Shai Kowal

Leonid Smolansky

Paul Marino

Yaron Hefetz

Benzion Sender

Garth D Hillman

Eitan Zmora

Aviram Sariel

Judah L Adelman

Nathan Baron

Tzvi Tzelnick

Eyal Melanmed-Cohen

Eyal Moses

Shimon Levit

Vered Machal

Yosefa Asaf

Sergio Liberman

An integrated VMM (vector-matrix multiplier) module, including an electro-optical VMM component that multiplies an input vector by a matrix to produce an output vector; and an electronic VPU (vector processing unit) that processes at least one of the input and output vectors. Various error reducing mechanisms are also discussed.

Vector-matrix multiplication

Dynamic RAM in a microprocessor system

A method and apparatus are provided for inserting an address at the beginning of a data stream that is being transferred through a FIFO buffer (65). The address is inserted at the beginning of the data stream to prevent the address from being lost. An address decoder (102) is used to identify a range of addresses that can access the FIFO buffer (65). The address may also contain header information for determining the destination of the data stream in a data processing system (20), and also contain information for controlling how the data stream is to be processed in the data processing system (20).

Apparatus and method for inserting an address in a data stream through a

An adjustable depth/width FIFO buffer (65) is provided that accommodates variable width data transfers. The FIFO buffer (65) has two sections of read/write registers (73, 75) that are each independently controlled for transferring 16 bit words or 32 bit words without wasting register space in the FIFO buffer (65) when transferring 16 bit words. When the FIFO buffer (65) is narrowed to transfer 16 bit words, the storage space is deepened. This allows maximum use of the FIFO buffer registers (72) when interfacing either 16 bits of parallel data or 32 bits of parallel data. The FIFO buffer (65) is a slave only buffer to a host processor, therefore, the FIFO buffer (65) cannot initiate output of data, keeping the design simple and small.

Adjustable depth/width FIFO buffer for variable width data transfers

A data ALU (arithmetic logic unit) (54) in a data processing system (20) performs both 24-bit arithmetic, and 16-bit exact arithmetic (including shifting and logical operations) using the same hardware. For a multiply/accumulate operation in 16-bit exact mode, shifting operations are used to align the operands so that 16-bit exact mode is transparent to a user. An entire instruction set can be executed in 24-bit mode or 16-bit exact mode. The same instructions and hardware are used in both modes. A transition between modes is performed by changing a status bit (97) in a status register (95).

Apparatus and method for performing both 24 bit and 16 bit arithmetic

An integrated circuit chip includes a processor (4) and a memory (10) coupled by data and address buses (PAB, PDB). The memory is switchable between a first, standard, mode of operation in which a memory controller (14) is operative and a second, cache, mode of operation in which a cache controller (12) is operative by a switch (16, 22, 40). A memory area includes a valid bits array (VBA), a bit of which is set when a valid word is stored in a respective memory address of the memory in standard mode. If a valid bit exists corresponding to an address on the address bus, then information loaded into the memory in standard mode can be used by the processor in cache mode. The operating mode of the memory is switched using an operating mode register having a cache enable section, and a cache enable control line coupled to the memory. A reset arrangement is provided for resetting the valid bits array to flush the cache in a single operation. In one preferred embodiment, the cache is an instruction cache and the integrated circuit chip is a digital signal processor (DSP).

Real time cache implemented by on-chip memory having standard and cache

Growing community of inventors

Rosh-Ha′ayin, Israel

Avner Goren