Samsung Electronics Co., Ltd.

Qualcomm Incorporated

Designart Networks Ltd

Samsung Israel Research Corporation

Avner Dor

Jun Jin Kong

Yaron Shany

Elona Erez

Moshe Twitto

Amit Berman

Ariel Doubchak

Shay Landis

Jun-Jin Kong

Yoav Shereshevski

Assaf Touboul

Oz Barak

Tal Philosof

Hong Rak Son

Jong-Won Lee

Hong-Rak Son

Evgeny Blaichman

Pil Sang Yoon

Chang Kyu Seol

Maxim Gotman

Eran Hof

Jung Soo Chung

Michael Erlihson

Shmuel Dashevsky

Young-Geon Yoo

Michael Kara-Ivanov

Eran Richardson

Moshe Ben Ari

Dashevsky Shmuel

Elik Almog Sheffi

Systems, devices, and methods for encoding information bits for storage, including obtaining information bits; encoding the information bits using an inner code to obtain a plurality of inner code words; encoding the plurality of inner code words using an outer code to generate an outer code word; and storing the outer code word in a storage device, wherein at least one of the inner code and the outer code includes a generalized concatenated code (GCC), and wherein the outer code word includes a hierarchical-GCC (H-GCC) code word.

Generalized hierarchical concatenated codes with fixed dimension and code length

A method of correcting data stored in a memory device includes: applying an iterative decoder to the data; determining a total number of rows in first data the decoder attempted to correct; estimating first visible error rows among the total number that continue to have an error after the attempt; estimating residual error rows among the total number that no longer have an error after the attempt; determining second visible error rows in second data of the decoder that continue to have an error by permuting indices of the residual error rows according to a permutation; and correcting the first data using the first visible error rows.

Encoding and decoding of data using generalized LDPC codes

A soft-decision decoding computes a first syndrome polynomial in accordance with a received word, computes a second syndrome polynomial by multiplying the first syndrome polynomial by a locator polynomial based on locations of erasures within the received word, finds a basis and private solution to an affine space of polynomials that solve key equations based on the second syndrome polynomial, determines a weak set of a locations of symbols in the received word with confidence below a certain confidence level, computes a matrix from the basis, the private solution and the weak set, determines sub-matrices in the matrix whose rank is equal to a rank of the matrix, determines error locator polynomial (ELP) candidates from the sub-matrices, the basis, and the private solution, and corrects the received word using a selected one of the ELP candidates.

Soft reed-solomon decoder for a non-volatile memory

A method for Bose-Chaudhuri-Hocquenghem (BCH) soft error decoding includes receiving a codeword x, wherein the received codeword x has &#x3c4;=t+r errors for some r&#x2265;1; computing a minimal monotone basis {&#x3bb;(x)}&#x2286;F[x] of an affine space V={&#x3bb;(x)&#x3f5;F[x]: &#x3bb;(x)&#xb7;S(x)=&#x3bb;'(x) (mod x), &#x3bb;(0)=1, deg(&#x3bb;(x)&#x2264;t+r}, wherein &#x3bb;(x) is an error locator polynomial and S(x) is a syndrome; computing a matrix A&#x2261;(&#x3bb;&#x3b2;)), wherein W={&#x3b2;, . . . , &#x3b2;} is a set of weak bits in x; constructing a submatrix of r+1 rows from sub matrices of r+1 rows of the subsets of A such that the last column is a linear combination of the other columns; forming a candidate error locating polynomial using coefficients of the minimal monotone basis that result from the constructed submatrix; performing a fast Chien search to verify the candidate error locating polynomial; and flipping channel hard decision at error locations found in the candidate error locating polynomial.

BCH fast soft decoding beyond the (d-1)/2 bound

A method of performing division operations in an error correction code includes the steps of receiving an output &#x3c9;&#x2208;F&#x2020;{0} wherein F=GF(2) is a Galois field of 2elements, &#x3c9;=&#x3a3;&#x3b2;&#xd7;&#x3b1;wherein &#x3b1; is a fixed primitive element of F, and &#x3b2;&#x2208;GF(2), wherein K=GF(2) is a subfield of F, and {1, &#x3b1;} is a basis of F in a linear subspace of K; choosing a primitive element &#x3b4;&#x2208;K, wherein &#x3c9;=&#x3c9;+&#x3b1;&#xd7;&#x3c9;, &#x3c9;=&#x3a3;&#x3b3;&#xd7;&#x3b4;&#x2208;K, &#x3c9;=&#x3a3;&#x3b3;&#xd7;&#x3b4;&#x2208;K, and &#x3b3;=[&#x3b3;, . . . , &#x3b3;]&#x2208;GF(2); accessing a first table with &#x3c9;to obtain &#x3c9;=&#x3c9;, computing &#x3c9;&#xd7;&#x3c9;in field K, accessing a second table with &#x3c9;=&#x3c9;to obtain (1+&#x3b1;&#xd7;&#x3c9;&#xd7;&#x3c9;)=&#x3c9;+&#x3b1;&#xd7;&#x3c9;, wherein &#x3c9;=(&#x3c9;&#xd7;(1+&#x3b1;&#xd7;&#x3c9;&#xd7;&#x3c9;))=&#x3c9;&#xd7;(&#x3c9;+&#x3b1;&#xd7;&#x3c9;)=&#x3c9;&#xd7;&#x3c9;+&#x3b1;&#xd7;&#x3c9;&#xd7;&#x3c9;; and computing products &#x3c9;&#xd7;&#x3c9;and &#x3c9;&#xd7;&#x3c9;to obtain &#x3c9;=&#x3a3;&#x3b8;&#xd7;&#x3b4;+&#x3b1;&#xb7;&#x3a3;&#x3b8;=&#x3b4;where &#x3b8;&#x2208;GF(2).

Low-power error correction code computation in GF (2R)

Systems and methods are described for low power error correction coding (ECC) for embedded universal flash storage (eUFS) are described. The systems and methods may include identifying a first element of an algebraic field; generating a plurality of lookup tables for multiplying the first element; multiplying the first element by a plurality of additional elements of the algebraic field, wherein the multiplication for each of the additional elements is performed using an element from each of the lookup tables; and encoding information according to an ECC scheme based on the multiplication.

Low power ECC for eUFS

A method for storing data within a memory device includes receiving data to be stored. The received data is encoded. The encoded data is stored within the memory device. Encoding the received data includes encoding the data into two or more sub-codewords. Each of the two or more sub-codewords includes a plurality of outer codewords. Two or more of the plurality of outer codewords are grouped to form a larger codeword that is larger than each of the plurality of outer codewords and the larger codeword is constructed to correct errors and/or erasures that are not correctable by the plurality of outer codewords, individually.

Generalized concatenated error correction coding scheme with locality

A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.

Nonvolatile memory devices and methods of controlling the same

A method of operating a storage device including a nonvolatile memory can be provided by receiving, from a host, address change information including changing logical addresses for data to be stored in the nonvolatile memory. Physical addresses can be sequentially allocated to the changing logical addresses included in the address change information to provide a first journal. A portion of at least one physical address allocated to the changing logical addresses can be removed to provide a second journal and the second journal can be stored in the nonvolatile memory.

Storage devices including logical to physical address mapping and methods of operating

A method of encoding generalized concatenated error-correcting codes includes providing a parity matrix {tilde over (H)}of a j-th layer code and predefined syndrome {tilde over (s)} of length n&#x2212;{tilde over (k)}, where the first n-kcoordinates are zero, n is a length of a codeword c of a first layer BCH code Cof dimension {tilde over (k)}, codeword c satisfies {tilde over (H)}c={tilde over (s)}, a first layer code includes only a BCH code, and each subsequent layer includes a Reed-Solomon (RS) stage followed by a BCH code; finding a square matrix R, of dimension (n&#x2212;{tilde over (k)})(n&#x2212;{tilde over (k)}) such that R{tilde over (H)}=(A|I), where A is an arbitrary matrix, R=(Q|T), where Q has n&#x2212;kcolumns Tand has k&#x2212;{tilde over (k)}columns; finding a vector c&#x2212;(a b) where a is a vector of length {tilde over (k)}and b is a vector of length n&#x2212;{tilde over (k)}; and solving where a=0 and b=Ts, and codeword c is nonzero only on the last n&#x2212;{tilde over (k)}=n&#x2212;kbits.

Bose-chaudhuri-hocquenchem (BCH) encoding and decoding tailored for redundant array of inexpensive disks (RAID)

A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vectorof a new stage 0 binary BCH codewordover a field GF(2) that comprises &#x394;t syndromes of length m bits, wherein the syndrome vectorcomprises l-th Reed-Solomon (RS) symbols of &#x394;t RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n&#x2212;1; and multiplyingby a right submatrix &#x168; of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by t, wherein the new binary BCH codeword is=&#x168;&#xb7;.

Efficient generalized tensor product codes encoding schemes

A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.

A flash memory device includes physical pages that store data sectors therein. The method of operating the flash memory device includes receiving write data sectors to be stored in the flash memory device, pairing the write data sectors with write data sectors and with written data sectors previously stored in physical pages of the flash memory device based upon a matching and deduplication operation to define data sector pairs and a difference therebetween, and rewriting to the physical pages of the flash memory device, in a partial-page writing mode, to store the difference between the write data sector and its respective paired data sector. The partial-page writing mode is performed on a respective physical page after a previous programming and before erasing. The written data sectors included in the data sector pairs only partially occupy the corresponding physical page of the flash memory device. The difference between the write data sector and its respective paired data sector is stored in an unoccupied portion of the corresponding physical page of the flash memory device.

Flash memory device including deduplication, and related methods

A memory system includes a memory controller; and a memory device, the memory device including a memory cell array, the memory cell array including least a first memory page having a plurality of memory cells storing a plurality of stored bits, the memory controller being such that, the memory controller performs a first hard read operation on the first memory page to generate a plurality of read bits corresponding to the plurality of stored bits, and if the memory controller determines to change a value of one of a first group of bits, from among the plurality of read bits, the memory controller selects one of the first group of bits based on log likelihood ratio (LLR) values corresponding, respectively, to each of the first group of bits, and changes the value of the selected bit.

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Kfar Saba, Israel

Avner Dor