Mellanox Technologies, Ltd.

Retym, Inc.

Aviv Berg

Ran Ravid

Lavi Koch

Chen Gaist

Dotan David Levi

Shai Cohen

Johan Jacob Mohr

Ran Sela

Eyal David

Daniel Kedar

Stanislav Gurtovoy

Roee Eitan

Yaakov Dayan

Yosi Sanhedrai

Esther T Fridman

Kirill Blum

A comparator circuit with a speed control element is disclosed herein. The speed control element may include a variable voltage source and one or more transistors. Using a voltage supplied by the variable voltage source, the one or more transistors may control a swing of a clock signal to provide a swing controlled clock signal to an amplification portion of the comparator circuit. The swing controlled clock therefor may be used to control the speed of the comparator circuit (e.g., an amplification phase) based on a level of noise in the circuit. The swing controlled clock may further be used to align an output common voltage of the comparator circuit with switching voltages of downstream logic cells (e.g., inverters) connected to the comparator circuit.

Comparator circuit with speed control element

In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.

Synthesized clock synchronization between network devices

In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.

A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.

Synthesized clock synchronization between networks devices

Embodiments are disclosed for channel estimation in a receiver of a communication system. An example method includes receiving, via a receiver of a communication system, an input signal. The example method further includes using a first event indicator embedded in an analog circuit of the receiver to slice the input signal to generate a sliced input signal and applying an offset to the input signal to generate an offsetted signal. The example method further includes using a second event indicator embedded in the analog circuit to slice the offsetted signal to generate a sliced offsetted signal. The example method further includes applying a first predefined delay to the sliced input signal and applying a second predefined delay to the sliced offsetted signal. The example method further includes generating a conditional ones signal based on the sliced input signal and the sliced offsetted signal and using the conditional ones signal to calibrate an equalizer embedded in the receiver.

Method and apparatus for blind channel estimation

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Beit Keshet, Israel

Aviv Berg