Centipede Semi Ltd.

Avishai Tvila

Alberto Mandler

A processor includes a pipeline and a multi-bank Branch-Target Buffer (BTB). The pipeline is configured to process program instructions including branch instructions. The multi-bank BTB includes a plurality of BTB banks and is configured to store learned Target Addresses (TAs) of one or more of the branch instructions in the plurality of the BTB banks, to receive from the pipeline simultaneous requests to retrieve respective TAs, and to respond to the requests using the plurality of the BTB banks in the same clock cycle.

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Giv′at-Shmuel, Israel

Avishai Tvila