International Business Machines Corporation

Avishai Moshe Fedida

Oz Dov Hershkovitz

Michal Rimon

Olaf Knute Hendrickson

Silvia Melitta Mueller

Gal Ashour

Karen Holtz

Ofer Peled

Adi Dagan

Craig T Atherton

Ofek Gutman

Craig Atherton

A computer system, computer readable storage medium, and computer-implemented method for retrograding an instruction stream to enhance random test generation. The method includes generating a test case for a design-under-test (DUT) comprising positioning one or more placeholder instructions in the test case. The method also includes identifying one or more benefiting instructions. The method further includes executing the test case by replacing the one or more placeholder instructions with one or more respective retrograding instructions. The one or more retrograding instructions influence the one or more benefiting instructions.

Instruction stream retrograding to enhance random test generation

Embodiments of the present disclosure are directed to an efficient and uniform process for generating multiple outputs for different generated test cases for an input request that share a common section in a pseudo-random software system. An enhanced disclosed method comprises processing an input request and a sequence of instructions until a state or condition of interest is reached in a first process. The condition of interest is marked as a split point in the first process. At the split point, a next process for generating multiple outputs is created to include a common section of the first process from the input request to the split point, an added form of randomization, and at least one instruction after the split point. The common section is generated only once in the first process, which can provide significantly enhanced performance.

Uniform process for generating multiple outputs with common section in pseudo-random software system

Validating microprocessor instruction execution by receiving a floating-point exception selection, receiving a validation method selection, generating validation data according to the floating-point exception selection and the validation method selection by randomly generating a first tensor element value and randomly generating a second tensor element value according to the first tensor element value and the floating-point exception selection, and executing a floating-point computation according to the validation data.

Validating microprocessor performance

A method and apparatus are provided for implementing random content of program loops in random test generation for processor verification. A converged branch instruction stream is used by a test generator to ensure that all random conditional branches converge to a main program loop. A built in exception handling mechanism of the test generator enables program interrupts to converge to the main program loop. Mandatory read only registers applied to the test generator allow all register based storage addresses to use registers that maintain a value and thus stabilize the storage address translations through subsequent iterations of the loop. A global class restriction mechanism defines specific restricted instruction classes applied to the test generator avoids inherently problematic operations for the program loops. Machine state detection and restoration mechanisms in the test generator are provided to preserve storage addressability.

Implementing random content of program loops in random test generation for processor verification

A method and apparatus are provided for implementing automated memory address recording in constrained random test generation for verification of processor hardware designs. A test generation program includes a built in feature to keep track of storage addresses used and to make the addresses available to the test definition. This built in feature of a constrained random test generator allows storage addresses used in the past to be accessed by the current instruction generation eliminating the requirement of deliberately establishing target addresses first. This allows separate test events to interact with the same storage addresses without having to write a special test.

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Gesher HaZiv, Israel

Avishai Moshe Fedida