General Electric Company

University of Arkansas

Microsemi Corporation

Avinash Srikrishnan Kashyap

Peter Micah Sandvik

Emad Andarawis Andarawis

David Mulford Shaddock

Stephen Daley Arthur

Alexander Viktorovich Bolotnikov

Ljubisa Dragoljub Stevanovic

Rui Zhou

Vinayak Tilak

James Jay McMahon

Joe Walter Kirstein

Harry Kirk Mathews, Jr

Peter Almern Losee

Christopher Fred Keimel

Reza Ghandi

David Alan Lilienfeld

Aaron Jay Knobloch

Dumitru Sdrulla

Stanislav Ivanovich Soloviev

H Alan Mantooth

Victor Mario Torres

Christian M Giovanniello

Mark Gerard Roberto

Peter Michah Sandvik

Harry Kirk Mathews

Jr Harry Kirk Mathews

A power transistor assembly and method of mitigating short channel effects in a power transistor assembly are provided. The power transistor assembly includes a first layer of semiconductor material formed of a first conductivity type material and a hard mask layer covering at least a portion of the first layer and having a window therethrough exposing a surface of the first layer. The power transistor assembly also includes a first region formed in the first layer of semiconductor material of a second conductivity type material and aligned with the window, one or more source regions formed of first conductivity type material within the first region and separated by a portion of the first region, and an extension of the first region extending laterally through the surface of the first layer.

Method and assembly for mitigating short channel effects in silicon carbide MOSFET devices

A surge suppression device includes a micro electromechanical system (MEMS) switch electrically connected to a current path. Additionally, the surge suppression device includes a transient voltage suppression (TVS) device electrically connected in series to the MEMS switch. The surge suppression device is configured to protect electronic components from voltage surges or current surges.

Low capacitance surge suppression device

A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

Method and system for a semiconductor device with integrated transient voltage suppression

A transient voltage suppression (TVS) device and a method of forming the device are provided. The transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer. The TVS device also includes a conductive path electrically coupled between the second layer and an electrical connection to a circuit external to the TVS device, the conductive path configured to permit controlling a turning on of the TVS device at less than a breakdown voltage of the TVS device.

Method and system for transient voltage suppression devices with active control

The present disclosure relates to a symmetrical, punch-through transient voltage suppression (TVS) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer. The mesa structure also includes beveled sidewalls forming mesa angles with respect to the semiconductor substrate and edge implants disposed at lateral edges of the second semiconductor layer. The edge implants including dopants of the second conductive-type are configured to cause punch-through to occur in a bulk region and not in the lateral edges of the second semiconductor layer.

Transient voltage suppression devices with symmetric breakdown characteristics

A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

Semiconductor assembly and method of manufacture

A method of fabricating an overvoltage protection device and an over-voltage circuit protection device are provided. The over-voltage circuit protection device includes a plurality of transient voltage suppression (TVS) devices coupled in electrical parallel.

Method and system for over-voltage protection using transient voltage suppression devices

A transient voltage suppression (TVS) device and a method of forming the device are provided. The TVS device includes a first layer of wide band-gap semiconductor material formed of a first conductivity type material, a second layer of wide band-gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, the second layer including a first concentration of dopant. The TVS device further including a third layer of wide band-gap semiconductor material formed of the second conductivity type material over at least a portion of the second layer, the third layer including a second concentration of dopant, the second concentration of dopant being different than the first concentration of dopant. The TVS device further including a fourth layer of wide band-gap semiconductor material formed of the first conductivity type material over at least a portion of the third layer.

Structure and method for transient voltage suppression devices with a two-region base

A transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (&#x3bc;m) and 22.0 &#x3bc;m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.

Method and system for transient voltage suppression

A high temperature electronic system includes an electronics unit configured for exposure to an environment having a temperature greater than approximately 150.0&#xb0; C. The remote electronics unit includes a transient voltage suppressor (TVS) assembly coupled in operative relationship with at least some electronic components of the electronics unit. The TVS assembly includes at least one TVS device comprising at least one of a punch-through wide band-gap semiconductor TVS die and an avalanche breakdown wide band-gap semiconductor TVS die encapsulated in a flip-chip package at least partially surrounding the die, and coupled to first and second electrodes exposed to a single side of the encapsulation.

Method and system for ultra miniaturized packages for transient voltage suppressors

A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon carbide (SiC), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

Over-voltage protection of gallium nitride semiconductor devices

A method of method of forming a wide band-gap semiconductor transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a connecting component configured to electrically couple a first electrical component to a second electrical component located remotely from the first electrical component through one or more electrical conduits and a transient voltage suppressor device positioned within the connecting component and electrically coupled to the one or more electrical conduits wherein the TVS device includes a wide band-gap semiconductor material.

Method and system for lightning protection with distributed transient voltage suppression

A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (&#x3bc;m) and 22.0 &#x3bc;m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.

A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The transient voltage suppressor (TVS) assembly includes a semiconductor die including a contact surface on a single side of the die, the die further including a substrate comprising a layer of at least one of an electrical insulator material, a semi-insulating material, and a first wide band gap semiconductor having a conductivity of a first polarity, at least a TVS device including a plurality of wide band gap semiconductor layers formed on the substrate; a first electrode coupled in electrical contact with the TVS device and extending to the contact surface, and a second electrode electrically coupled to the substrate extending to the contact surface.

Growing community of inventors

Niskayuna, NY, United States of America

Avinash Srikrishnan Kashyap