Cadence Design Systems, Inc.

Avinash Singh

Taranjit Singh Kukal

Surender Singh

Disclosed are mechanisms for implementing an IC package layout design with an integrated circuit package design estimator. These mechanisms determine an estimated number of layers for an integrated circuit (IC) package design including one or more IC die designs, determine whether the estimated number of layers suffice to accommodate routing demands for the IC package layout design, determine a power layer and/or a ground layer based in part or in whole upon one or more factors, and generate an output for the IC package layout design based using at least the estimated number of layers and the power layer and/or the ground layer. These mechanisms use input including connectivity information, thermal effects, and/or IC placement information to determine estimates for the total number of layers, layer stack-up, power and ground plane assignment, and via libraries to guide IC package layout design.

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Haryana, India

Avinash Singh