Intel Corporation

Avinash N Ananthakrishnan

Efraim Rotem

Doron Rajwan

Eliezer Weissmann

Jeremy J Shrall

Stephen H Gunther

Ankush Varma

Krishnakanth Venkata Sistla

Nadav Shulman

Alon Naveh

Ryan Donovan Wells

Martin Rowland

Eugene Gorbatov

Ian M Steiner

Matthew M Bace

Anupama Suryanarayanan

Hisham Abu-Salah

Inder M Sodhi

Vivek Garg

Chris Poirier

Chinmay Ashok

Jason W Brandt

Eric C Samson

Eric J DeHaemer

Anil Aggarwal

Dorit Shapira

Gaurav Khanna

Xiuting C Man

Muhammad Abozaed

Ameya Ambardekar

Hang T Nguyen

Devadatta V Bodas

Jay D Schwartz

Thi Dang

Krishna K Rangan

Cyprian W Woo

Guy M Therien

Nir Rosenzweig

Russell Jerome Fenger

Michael N Derr

Brent Ralph Boswell

Tomer Ziv

Bryan L Spry

Daniel G Borkowski

Arik Gihon

Mark Rowland

Don Soltis

Aimee D Wood

Eric R Heit

Deepak M Rangaraj

Marcus W Song

Joseph R Doucette

Robert J Hayes

Adam E Letendre

Craig Topper

Joseph M Alberts

Praveen Kumar Gupta

Eliezer Wiessman

Vedvyas Shanbhogue

Ravishankar Iyer

Andrew J Herdrich

Alexander Gendler

James G Hermerding, Ii

Ashok Raj

Dan Baum

Kai Cheng

Ashish V Choubal

Viktor D Vogman

Rameshkumar G Illikkal

Jorge Pedro Rodriguez

Shaun M Conrad

Hisham Abu Salah

Nikhil Gupta

Edward R Stanford

Jaideep Moses

Brian J Griffith

Kosta Luria

Itai Feit

Sadagopan Srinivasan

Kameswar Subramaniam

Monica Gupta

Craig S Forbell

Sudheer Nair

Vijay Dhanraj

Israel Hirsh

Nimrod Angel

Ido Melamed

Eric Dehaemer

Ronny Korner

Vijay S R Degalahal

Jared E Bendt

Gary A Andrew

Cesar A Quiroz

Gopikrishna Jandhyala

David Pawlowski

Tamir Salus

Rachid Rayess

Natanel Abitan

Assaf Ganor

Celeste M Brown

An apparatus is provided, where the apparatus includes a plurality of components, wherein an individual component has a corresponding throttling priority of a plurality of throttling priorities. The apparatus further includes logic to selectively throttle one or more of the plurality of components. In an example, an order in which the one or more of the plurality of components are to be throttled may be based on the plurality of throttling priorities.

Throttling of components using priority ordering

In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

Multi-level loops for computer processor control

In one embodiment, a processor includes: a plurality of cores; a first storage to store parameter information for a voltage regulator to couple to the processor via a voltage regulator interface; and a power controller to control power consumption of the processor. The power controller may determine a performance state for one or more cores of the processor and include a hardware logic to generate a message for the voltage regulator based at least in part on the parameter information, where this message is to cause the voltage regulator to output a voltage to enable the one or more cores to operate at the performance state. Other embodiments are described and claimed.

Techniques to enable communication between a processor and voltage regulator

In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.

System, apparatus and method for providing hardware state feedback to an operating system in a heterogeneous processor

Embodiments are generally directed to enhanced power management for support of priority system events. An embodiment of a system includes a processing element; a memory including a registry for information regarding one or more system events that are designated as priority events; a mechanism to track operation of events that requires Turbo mode operation for execution; and a power control unit to implement a power management algorithm. The system is to maintain an first energy budget and a second residual energy budget for operation in a Turbo power mode, and wherein the power management algorithm is to determine whether to authorize execution of a detected system event in the Turbo power mode based on the second residual energy budget upon determining that the first energy budget is not sufficient for execution of the detected system event and that the detected system event is designated as a priority event. Priority designations for the priority events may include a first High Priority designation and a second Critical designation.

Enhanced power management for support of priority system events

In one embodiment, an apparatus comprises: a plurality of intellectual property (IP) circuits, each of the plurality of IP circuits including a configuration register to store a dynamic current budget; and a power controller coupled to the plurality of IP circuits, the power controller including a dynamic current sharing control circuit to receive current throttling hint information regarding a workload to be executed on at least some of the plurality of IP circuits and generate the dynamic current budget for each of the plurality of IP circuits based at least in part thereon. Other embodiments are described and claimed.

System, apparatus and method for dynamically controlling current consumption of processing circuits of a processor

An apparatus is provided, where the apparatus includes a plurality of processing cores to execute a plurality of processes, a register to store an indicator that is to indicate a preference for either performance or energy efficiency, a first circuitry to determine an effective utilization of a first processing core, based on the indicator, and a second circuitry to select at least one of an operating voltage or an operating frequency of the first processing core, based at least in part on the effective utilization of the first processing core.

Per-core operating voltage and/or operating frequency determination based on effective core utilization

In one embodiment, a processor includes a plurality of cores and a power controller. This power controller in turn may include a voltage ramp logic to pre-empt a voltage ramp of a voltage regulator from a first voltage to a second voltage, responsive to a request for a second core to exit a low power state. Other embodiments are described and claimed.

Processor to pre-empt voltage ramps for exit latency reductions

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Portland, OR, United States of America

Avinash N Ananthakrishnan