Innovium, Inc.

Alcatel-lucent USA Inc.

Avinash Gyanendra Mani

Mohammad Kamel Issa

Neil Barrett

William Brad Matthews

Ajit Kumar Jain

Bruce Hui Kwan

Ashwin Alapati

Puneet Agarwal

Gregory S Mathews

Srinivas Gangam

Sanjay Jain

Patrick James Bourke

Michael John Filardo

Jorge Alejandro Aguilar

Anurag Kumar Jain

Approaches, techniques, and mechanisms are disclosed for efficiently buffering data units within a network device. A traffic manager or other network device component receives Transport Data Units ('TDUs'), which are sub-portions of Protocol Data Units (“PDUs”). Rather than buffer an entire TDU together, the component divides the TDU into multiple Storage Data Units (“SDUs”) that can fit in SDU buffer entries within physical memory banks. A TDU-to-SDU Mapping (“TSM”) memory stores TSM lists that indicate which SDU entries store SDUs for a given TDU. Physical memory banks in which the SDUs are stored may be grouped together into logical SDU banks that are accessed together as if a single bank. The TSM memory may include a number of distinct TSM banks, with each logical SDU bank having a corresponding TSM bank. Techniques for maintaining inter-packet and intra-packet linking data compatible with such buffers are also disclosed.

Efficient buffer utilization for network data units

Network chip utility is improved using multi-core architectures with auxiliary wiring between cores to permit cores to utilize components from otherwise inactive cores. The architectures permit, among other advantages, the re-purposing of functional components that reside in defective or otherwise non-functional cores. For instance, a four-core network chip with certain defects in three or even four cores could still, through operation of the techniques described herein, be utilized in a two or even three-core capacity. In an embodiment, the auxiliary wiring may be used to redirect data from a Serializer/Deserializer ('SerDes') block of a first core to packet-switching logic on a second core, and vice-versa. In an embodiment, the auxiliary wiring may be utilized to circumvent defective components in the packet-switching logic itself. In an embodiment, a core may utilize buffer memories, forwarding tables, or other resources from other cores instead of or in addition to its own.

Network chip yield improvement architectures and techniques

Approaches, techniques, and mechanisms are disclosed for efficiently buffering data units within a network device. A traffic manager or other network device component receives Transport Data Units ('TDUs'), which are sub-portions of Protocol Data Units ('PDUs'). Rather than buffer an entire TDU together, the component divides the TDU into multiple Storage Data Units (&#x201c;SDUs&#x201d;) that can fit in SDU buffer entries within physical memory banks. A TDU-to-SDU Mapping (&#x201c;TSM&#x201d;) memory stores TSM lists that indicate which SDU entries store SDUs for a given TDU. Physical memory banks in which the SDUs are stored may be grouped together into logical SDU banks that are accessed together as if a single bank. The TSM memory may include a number of distinct TSM banks, with each logical SDU bank having a corresponding TSM bank. Techniques for maintaining inter-packet and intra-packet linking data compatible with such buffers are also disclosed.

The technology described in this document can be embodied in an integrated circuit device comprises a first data processing unit comprising one or more input ports for receiving incoming data, one or more inter-unit data links that couple the first data processing unit to one or more other data processing units, a first ingress management module connected to the one or more inter-unit data links, the first ingress management module configured to store the incoming data, and forward the stored data to the one or more inter-unit data links as multiple data packets, and a first ingress processing module. The integrated circuit device also comprises a second data processing unit comprising one or more output ports for transmitting outgoing data, and a second ingress management module connected to the one or more inter-unit data links.

High-throughput multi-node integrated circuits

A memory system for a network device is described. The memory system includes a main memory configured to store one or more data elements. Further, the memory system includes a link memory that is configured to maintain one or more pointers to interconnect the one or more data elements stored in the main memory. The memory system also includes a free-entry manager that is configured to generate an available bank set including one or more locations in the link memory. In addition, the memory system includes a context manager that is configured to maintain metadata for a list of the one or more data elements.

System and method for enabling high read rates to data element lists

Methods and apparatus for transmit buffers for network devices. One apparatus includes a packing unit, a buffer manager and a plurality of aggregated port buffers, each coupled to receive output from the packing unit. The packing unit is configured to receive packet data as input segments of a first size; generate storage units of a second size; and write each storage unit to a particular aggregated port buffer identified by the buffer manager. The buffer manager is configured to: select a particular aggregated port buffer for each storage unit, and send information to the buffer manager about the selected particular aggregated port buffer; monitor availability of storage space in the aggregated port buffers; control reception of input segments based on storage space availability; and manage transmission of the storage units from the aggregated port buffers to one or more external destinations as output segments of a third size.

Transmit buffer device for operations using asymmetric data widths

A memory system for a network device is described. The memory system includes a packing data buffer including a plurality of memory banks arranged in a plurality of rows and a plurality of columns. The packing data buffer is configured to store incoming data elements of a plurality of widths in the plurality of memory banks. The memory system also includes a free address manager configured to generate an available bank set based on one or more free memory banks in the plurality of memory banks. And, the memory system includes distributed link memory configured to maintain one or more pointers to interconnect a set of one or more memory locations of the one or more memory banks in the packing data buffer to generate at least one list.

System and methods for flexible data access containers

A memory system for a network device is described. The memory system includes a main memory configured to store one or more data elements. Further, the memory system includes a parent distributed-linked list configured to store linked-list metadata. And, the memory system includes a child distributed-linked list configured to maintain list metadata to interconnect the one or more data elements stored in the main memory to generate at least a first snapshot, said linked-list metadata references the snapshot.

Growing community of inventors

San Jose, CA, United States of America

Avinash Gyanendra Mani