Freescale Semiconductor,inc.

Avinash Chandra Tripathi

Sanjay Kumar Wadhwa

Krishna Thakur

Deependra Kumar Jain

Anand Kumar Sinha

Devesh P Singh

A level shifter that shifts a voltage level of an input signal, where the input signal oscillates between a voltage level of a first supply voltage and ground. The level shifter includes a bias circuit, and first and second transistors. The bias circuit provides a bias voltage to the first transistor based on the first supply voltage. The second transistor is connected in series with the first transistor, and the series combination is connected between voltage supplies that provide second and third supply voltages. The second transistor receives the input signal at its gate, and a level-shifted version of the input signal is output at a node between the first and second transistors. The level-shifted signal oscillates between the voltage levels of the second and third supply voltages.

Level shifter with low duty cycle variation

A buffer circuit includes an inverter and a level-shifter. The inverter receives a first oscillating signal at a first voltage level and generates an inverted version of the first oscillating signal at a second voltage level. The level-shifter receives a second oscillating signal at a third voltage level, which has a phase difference from the first oscillating signal, and the inverted first oscillating signal, and generates a buffer output signal at a fourth voltage level.

Buffer circuit for voltage controlled oscillator

An integrated circuit with a testable power-on-reset (POR) circuit includes a voltage divider, an inverter, a level-shifter, a buffer and a flip-flop. The voltage divider receives a first supply voltage and generates a second supply voltage. The POR circuit receives the second supply voltage and generates a POR voltage signal when the second supply voltage exceeds a POR de-assertion threshold. The level-shifter receives the POR voltage signal and an inverted POR voltage signal from the inverter circuit and generates a level-shifted POR voltage signal at a voltage level of the first supply voltage. The buffer receives the level-shifted POR voltage signal and outputs a delayed level-shifted POR voltage signal. The flip-flop receives the first supply voltage as data input, the delayed level-shifted POR voltage signal as clock input, the level-shifted POR voltage signal as reset input, and outputs a voltage-monitor signal at the voltage level of the first supply voltage.

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Noida, India

Avinash Chandra Tripathi