Faraday Technology Corporation

Aviles Chang

Wang-Jin Chen

A SIP (system in package) with a chip and a memory mode, capable of performing integration test on the memory module even if the memory module does not include any scan chain is provided. The chip has a built-in self-test (BIST) circuit, which generates test pattern signals to test the memory module in response to a mode signal. Under a test mode, after the memory module receives the test pattern signals, the memory module outputs responsive readout signals to the BIST circuit and the BIST circuit determines and outputs a test result and a test record in response to the readout signals. If the test fails, conditions of the faulty memory module are recognized from the test record.

Growing community of inventors

Hsinchu County, Taiwan

Aviles Chang