International Business Machines Corporation

Avijit Saha

Nadeem Malik

Richard James Eickemeyer

Walid M Kobrosly

Chandrasekhar Narayanaswami

Murthy V Devarakonda

Timothy Alan Dietz

Jimmy Paul Strickland

Charles Gorham Ward

Jack P Gelb

Alan Vicha Pita

Zhongru Julia Lin

Douglas Craig Bossen

Brian Walter O'Krafka

Shih-Hsiung Stephen Tung

Kevin Arthur Chiarot

Marques Benjamin Quiller

Shahram Salamian

Subhash Rasiklal Vohra

Brett Adam St Onge

James D Christian

Namratha Rajasekharaiah Jaisimha

Manratha Rajasekharaiah Jaisimha

Greg N Fife

William M Canfield

Lisa A Curb

Mehrdad Soheili-Arasi

The creator or author of the Web document or page at the Web site source of the page is enabled to prioritize all of the hyperlinks to other Web documents embedded in the Web page in order to optimize the needs such as the business needs of the host. The prioritization is applied in the determination of the order in which the Web documents linked to the activated embedded hyperlinks in the Web document are to be accessed. The system is implemented through the inclusion of a hypertext markup language tag associated with each of the prioritized hyperlinks indicative of the priority level of the associated hyperlink. The implementation for designating a priority level for each of the hyperlinks may be enabled to change any previously designated priority levels for said hyperlinks. Such changes in any previously designated priority levels could be made applicable to the priority levels in previously distributed copies of said Web document.

Assigning priority levels to hyperlinks embedded in the created Web documents

The user requesting the search is enabled to analyze the list of excessive hits in a manner organized through a Web content manager on the user's display screen, and reduce the excessive hits through the elimination of extraneous domains or subdomains captured by the search. An implementation for reducing an excessive number of hits in a search result received at one of the receiving display stations on the Web comprising conventional means for displaying at said receiving display station, Web documents received from sources on the Web, and means for conducting keyword searches on the Web. There are means associated with the receiving display stations for displaying the number of Web documents hit by said keyword searches, together with means, responsive to an excessive number of Web document hits, for enabling a user to display a hierarchical level of the domains of the Web documents hit by said searches with a count of the number of hits for each domain, and means enabling the user to interactively eliminate selected domains to thereby reduce the excess number of hits in said search.

System for conducting searches on the world wide web enabling the search requester to modify the domain context of a search responsive to an excessive number of hits on combinations of keywords

Provided are data structures for use in storing data. A plurality of data structures are defined in a computer readable medium, wherein each data structure indicates a plurality of attributes and at least one function of a storage resource to store data. Policies are defined in the computer readable medium that associate data characteristics to data structures based on a correspondence of data characteristics and the attributes defined in the data structures, wherein each defined data structure is adapted to provide requirements to determine a storage resource to store associated data, and wherein the defined data structure is adapted to provide the storage resource with requirements for storing the data.

Method, system, and program for a policy based storage manager

Method for a policy based storage manager

Selecting the optimum service provider for each telephone call made so as to minimize the cost of each call. Each of the service providers is likely to be charging fees for calls at different rates determined by the measures of different sets of predetermined calling conditions that the provider sets up. An implementation for initiating a telephone call from the calling station to a selected receiving station, determining the measures of the predetermined calling conditions, determining the optimum service provider charging the minimum fee for the telephone call based on the determined measures of said service provider's set of predetermined calling conditions and routing the initiated telephone call to said receiving station through said optimum service provider.

Telecommunications system for minimizing fees paid to telecommunications service providers by selecting the optimum provider for each telephone call from a group of available providers based upon tracked measurements of different sets of conditions determining providers' fees

Monitoring of any conventional telephone conference in which a requisite set of conference attendees respectively at a corresponding set of telephone stations are connected into a telephone conference. In association with the telephone conference, a communication network with user access via a plurality of data processor controlled interactive display stations for displaying received network documents available from sources on the network in which there is an interactive display station associated with each of said set of telephone stations with a displayed document including an indicator representing each attendee having means for indicating whether the attendee's telephone station is connected into the conference, and means for indicating whether the attendee is speaking. During telephone conference initiation, there is placed on-call each telephone station initially connecting into the conference and there is an implementation for calling said on-call telephone stations into the conference when a quorum of said requisite attendees has connected into the conference.

Monitoring telephone conferences through a network of computer controlled display terminals, each associated with a telephone station and displaying a user-interactive monitoring page

A method and implementing system are provided in which processor registers are divided into sectors and such sectors are individually renamed. In one embodiment, the register file is divided into sectors such that the smallest accessible unit for an instruction set in each register can be uniquely addressed and renamed thereby providing additional effective registers for renaming.

Method and system for dividing a computer processor register into sectors

A method and system for dividing computer processor registers into sectors and storing frequently used data in the most significant unused sectors. The method includes sector renaming that is performed on each individual sector (i.e., on a sector-by-sector basis) rather than renaming an entire processor register. A register is divided into sectors such that the smallest accessible unit for an instruction in each register can be uniquely addressed and renamed. A register file is divided into sectors so that each process register can be uniquely addressed and renamed. The most significant sectors of the processor registers are used to hold pre-assigned values therein. Data previously loaded into processor register sectors is stored in the most significant sectors of the processor registers for possible future referencing and use. The method also includes establishing a sign-extend memory that includes at least one sign-extend bit in a sector status table.

Method and system for dividing a computer processor register into sectors and storing frequently used values therein

A method of handling a cache error (such as a parity error), which allows a software recovery, by reporting the error using an unrelated system resource, such as an interrupt service, and particularly a data storage interrupt. The parity error can be reported by generating a data storage interrupt and using the data storage interrupt status register (DSISR) to indicate that the data storage interrupt is a result of the parity error. The context of the processor can be fully synchronized while handling the parity error.

Recovery mechanism for L1 data cache parity errors

A method and apparatus is provided for enhanced error correction processing through a retry mechanism. When an L1 cache instruction line error is detected, either by a parity error detection process or by an ECC (error correcting code) or other process, the disclosed methodology will schedule an automatic retry of the event that caused the line error without re-booting the entire system. Thereafter, if the error remains present after a predetermined number of retries to load the requested data from L1 cache, then a second level of corrective action is undertaken. The second level corrective action includes accessing an alternate memory location, such as the L2 cache for example. If the state of the requested cache line is exclusive or shared, then an artificial L1 miss is generated for use in enabling an L2 access for the requested cache line. If the requested cache line still does not load from the L2 cache, the second level corrective methodology, after a selective number of retries, terminates and a machine check is generated to initiate a more extensive corrective or recovery action procedure. In an exemplary embodiment, a mechanism is illustrated for recovery from transient errors in an L1 cache load operation although the disclosed methodology may also be implemented partially or entirely in software and in any parity or other error detecting application.

Cache error retry technique

The present invention provides a system and method for verifying an integrated circuit model. The model includes a plurality of net variables. The system and method comprises generating a plurality of tests for simulating the integrated circuit, precalculating a reduced model based upon the generated tests, and evaluating the reduced model. In a preferred embodiment, the present invention includes restricting the test that are generated. Then net invariants for the integrated circuit are generated by translating the restricted plurality of tests to a smaller set of possible values for the net variables. Thereafter, a minimization algorithm or procedure is utilized to minimize the logic used in the particular system based upon the latch constraints. This system produces a reduced model which reduces the amount of the integrated circuit that must be simulated thereby increasing the simulation speed thereof. Accordingly, the present invention integrates an event-driven simulation and a cycle simulation in such a manner that the saving can be proportional to the size of the reduction of the model. In many environments this reduction is significant because it allows for a significant reduction in space which has a clear bearing on the verification process.

System and method for model size reduction of an integrated circuit

A method and implementing computer system is provided in which an internet or web network user may invoke a hyperlink or site link listing mode to retrieve only the hyperlinks available on selected target pages rather than retrieving the entire text and graphics of the target pages. The network assembles only the available hyperlinks and associated activation code segments for presentation to the user. The user may then select from the presented hyperlinks, the most appropriate hyperlink or path in pursuit of the user's particular search goals. The hyperlink access methodology enables faster navigation through selected and more direct paths to particular search goals by selectively assembling and displaying listings of only hyperlinks of designated target pages rather than entire page presentations. The user may designate and change the number of levels to be searched for hyperlinks, and displays are presented and organized so as to enable a user to quickly focus upon the sites most directly related to the user's search goals while requiring only minimal network usage time and reducing network traffic. The designated path through the chosen sites may be saved as a bookmarks for future reference and access.

Skeleton page retrieval mode for web navigation

A method and apparatus for reducing the number of cycles required to implement load instructions in a data processing system having a Central Processing Unit (CPU). The CPU includes a rename register file that can be used in whole or in part for retaining cache lines from previously executed load instructions. The rename register file is then used by subsequent instructions (e.g. load instructions) requiring the data previously loaded therein. Thus, reducing the cycles normally associated with retrieving the data from the cache for the subsequent instructions.

Growing community of inventors

Austin, TX, United States of America

Avijit Saha