Cypress Semiconductor Corporation

Mentor Graphics Corporation

Avijit Dutta

Mark A Kassab

Wu-Tung Cheng

Manish Sharma

Robert Brady Benware

Krishnan Anandh

Neil Tuttle

Janusz Rajski

Jerzy Tyszer

Nilanjan Mukherjee

Robert Douglas Thompson

Grzegorz Mrugalski

Haneef D Mohammed

Jakub Janicki

Andrew Price

Joseph P Skudlarek

Steven Danz

Ryan Morse

Mrugalski Grzegorz

Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling for testing a plurality of cores in a system on circuit. Test data are encoded to derive compressed test patterns that require small numbers of core input channels. Core input/output channel requirement information for each of the compressed test patterns is determined accordingly. The compressed patterns are grouped into test pattern classes. The formation of the test pattern classes is followed by allocation circuit input and output channels and test application time slots that may comprise merging complementary test pattern classes into clusters that can work with a particular test access mechanism. The test access mechanism may be designed independent of the test data.

Test scheduling with pattern-independent test access mechanism

Disclosed are representative embodiments of methods, apparatus, and systems for partitioning-based Test Access Mechanisms (TAM). Test response data are captured by scan cells of a plurality scan chains in a circuit under test and are compared with test response data expected for a good CUT to generate check values. Based on the check values, partition pass/fail signals are generated by partitioning scheme generators. Each of the partitioning scheme generators is configured to generate one of the partition pass/fail signals for one of partitioning schemes. A partitioning scheme divides the scan cells into a set of non-overlapping partitions. Based on the partition pass/fail signals, a failure diagnosis process may be performed.

Test access mechanism for diagnosis based on partitioning scan chains

Techniques for reducing post-routing delay variance are described herein. In an example embodiment, an initial netlist includes multiple instances that represent digital components of an electronic design. An base signature is assigned to each instance in the initial netlist, where the base signature is based on two or more design or connectivity attributes of the instance. The base signatures are then used to generate an initial instance ordering of the instances in the initial netlist. A subsequent netlist, different from the initial netlist but representing the same electronic design, is received. Base signatures are assigned to the instances on the subsequent netlist and a subsequent instance ordering is generated. The subsequent instance ordering preserves the same order as the initial instance ordering for those instances that are included in both the initial netlist and the subsequent netlist. In this manner, any later netlist-based processing (e.g., such as packing, placement, and routing) is shielded from the negative re-design effects caused by the subsequent changes to the initial netlist and, consequently, the post-routing timing delay variance of the electronic design is reduced.

Stability improvements for timing-driven place and route

A device includes a controller configured to provide a data word and check bits for the data word to decoding logic, the decoding logic configured to generate a decoding of the data word and check bits for the data word in conformance with an H-matrix having the following properties: (a) no all 0 columns; (b) all columns are distinct; (c) no linear dependency involving three or less columns; (d) no linear dependency involving columns C, C, C, C, where m&#x3e;k&#x3e;j&#x3e;i, where j=i+1 and m=k+1; and (e) no linear dependency involving columns C, C, C, C, where m&#x3e;k&#x3e;j&#x3e;i, where (j=i+1 and m&#x2212;k=q) or (k=j+1 and m&#x2212;i=q) or (m=k+1 and j&#x2212;i=q) for all integer values of q such that q&#x3e;1 and q&#x3c;=d, where d&#x3e;=2 and d&#x3c;=n&#x2212;1 where n&#x2212;k is a number of the check bits.

Low cost adjacent double error correcting code

Techniques for placement in highly constraint chip architectures are described herein. In an example embodiment, a computer system places a digital portion of an electronic design for a programmable chip. The programmable chip comprises multiple fixed-function blocks and a plurality of pins, where each one of the multiple fixed-function blocks can be coupled only to a respective subset of the plurality of pins. The electronic design comprises a particular fixed-function block (FFB) instance that is connected to a particular input-output (IO) instance. The computer system places (e.g., by using a backtracking search) the particular FFB instance on a particular fixed-function block and the particular IO instance on a particular pin from a particular subset of the plurality of pins, where in the programmable chip the particular fixed-function block can be coupled only to the particular subset of the plurality of pins.

Techniques for placement in highly constrained architectures

Test access mechanism for diagnosis based on partitioining scan chains

Growing community of inventors

Tigard, OR, United States of America

Avijit Dutta