Densbits Technologies Ltd.

Amazon Technologies, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Avigdor Segal

Hanan Weingarten

Avi Steiner

Erez Izenberg

Erez Sabbag

Igal Maly

Jonathan Cohen

Said Bshara

Ilan Bar

Eli Sterin

Leah Shalev

Anna Rom-Saksonov

Shadi Ammouri

Nitzan Zisman

Anthony Nicholas Liguori

Guy Nakibly

Leonid Baryudin

Michael Katz

Eric Samuel Stone

Clint Joseph Sbisa

Hani Ayoub

Matthew B Barr

Ofir Avraham Kanter

Noam Katz

Jonathan Chocron

Steven Anthony Kady

Se Wang Oh

Jonathan Welter Mullen

Noga Smith

Noam Attias

Nofar Mann

Steven Douglas Robinson

Vitaly Ostrovsky

Tal Avraham

Tatiana Cooke

Abhishek Katuluru

Saleh Abd-Alhaleem

Yossi Leybovich

Irena Shemesh

Yehuda Yitschak

Dror Fleischmann

Alik Vainerovitch

Guy Azrad

Boris Barsky

A wake-up management circuit for implementation in circuit boards with multiple processors is disclosed. The wake-up management circuit utilizes hardware resources to generate a wake-up signal for a processor in a low power mode when traffic intended for the processor is received by the wake-up management circuit. The wake-up management circuit is configured to generate a wake-up signal for a specific processor when address information in a data packet received by the wake-up management circuit indicates that the data packet is intended for the specific processor (e.g., the specific processor is the destination for the data packet).

Wake-up management circuit for multiple processors

Techniques for low-latency packet processing are disclosed. A network device receives a first set of write transactions including a first set of data segments corresponding to a first DMA descriptor from a host. The network device receives a second set of write transactions including a second set of data segments corresponding to a second DMA descriptor from the host. The network device detects that the first set of data segments have been written. In response to detecting that the first set of data segments have been written, and prior to completely writing the second set of data segments and to receiving a packet notifier from the host, the network device processes the first DMA descriptor.

Low-latency packet processing for network device

An integrated circuit for distributing processing tasks includes a pre-selector circuit and a scheduler circuit. The pre-selector circuit is configured to receive a processing task, determine a category of the processing task, and select, from a set of task distribution techniques and based at least in part on the category of the processing task, a task distribution technique for distributing the processing task to a group of processing units. The scheduler circuit is configured to implement the selected task distribution technique to select, from the group of processing units, a target processing unit for performing the processing task.

Processing unit selection mechanism

A networking manager of an extension server of a virtualized computing service detects that a data link layer frame has been obtained at the extension server. The networking manager delivers at least a portion of contents of the frame to a compute instance running at the extension server in response to determining that a destination media access control (MAC) address of the frame matches a MAC address of a local-premise-access virtual network interface attached to the compute instance. The local-premise-access virtual network interface is not assigned an Internet Protocol (IP) address from a range of IP addresses managed by the virtualized computing service.

Virtual network interfaces for managed layer-2 connectivity at computing service extension locations

Communication in an asymmetric multiengine system is handled using engine routing tables defining subsets of engines to control engine-to-engine connection mapping. Local devices perform an engine selection process that includes selecting an engine routing table based on a number of remote engines in a remote device and selecting an engine set from the selected table based on an identifier of the remote device. A connection to the remote device is created using the engines identified in the selected engine set.

Symmetric communication for asymmetric environments

The integrity of transmitted data can be protected by causing that data to be transmitted twice, and calculating protection information (PI) for the data from each transmission. The PI can include information such as a checksum or signature that should have the same value if the data from each transmission is the same. If the PI values are not the same, an error handling procedure can be activated, such as may retry the transmission. For write operations, the data can be transmitted twice from a source to a storage destination, while for read operations, the data can be transmitted to a recipient then sent back from the recipient to the storage device, with PI calculated for each transmission. A component such as a storage processor can perform at least this comparison step. Such approaches can also be used for network transmission or high performance computing.

Data integrity protection

A technique for packet processing may include maintaining a data structure representing transport status information associated with a sliding window of sequential packets for a host system. When a packet targeted for the host system is received, a packet validation process can be performed on the packet. The packet validation process may include validating that the packet belongs to the sliding window of the sequential packets by comparing the packet serial number of the packet against the packets being expected in the sliding window. The packet validation process may also include validating that the packet is being received for the first time and is not a duplicate packet. Upon validating the packet, the packet can be placed into the host system, and the status information can be updated to indicate that the packet has been received.

Packet serial number validation

A memory apparatus for detecting false hits in a content-addressable memory (CAM) is disclosed. The memory apparatus includes a controller coupled to the CAM and a memory. The controller receives a search result including an address from the CAM, the address corresponding to a matching entry from a first set of data entries that matches a search tag. The controller provides a read address based on the address to the memory, which returns a second data entry from a second set of data entries corresponding to the read address. The controller receives the read data and generates an error detection result based on a comparison between the second data entry and the search tag.

False hit detection in ternary content-addressable memory

A method that includes sending to an embedded flash storage device (EFSD) and during a transaction, a data unit and recovery metadata that differs from a flash memory unit memory management data structure (FMUMMDS); instructing the EFSD to program the data unit and the recovery metadata to a group of flash memory cells; sending to the host computer a transaction completion indication in response to a successful completion of the programming and before a completion of a management process that comprises updating by the flash memory controller, the FMUMMDS to reflect (a) the recovery metadata and (b) physical address information related to the group of the flash memory cells; and programming, by the EFSD, the FMUMMDS to the flash memory unit; wherein the data structure is reconstructible based upon the recovery metadata and the physical address information related to the group of the flash memory cells.

Programming an embedded flash storage device

According to an embodiment of the invention there is provided a method for accelerating programming of data, the method may include receiving multiple input data units that were sent from a host computer; wherein the input data units may include first and second input data units; first level programming the first input data units to cache memory pages and first level programming the second input data units to first level target memory pages; and applying a copy back operation that comprises retrieving the first input data units from the cache memory pages and second level programming the first input data units to second level target memory pages; wherein any target page out of the first level target pages and the second level target pages differs from a cache memory page; and wherein the first level programming is faster than the second level programming.

Accelerating programming of a flash memory module

A method for fast decoding, the method may include (a) performing a hard read of a group of flash memory cells to provide hard read data; wherein the group of flash memory cells store a codeword that comprises component codes of multiple dimensions; (b) hard decoding the hard read data to provide a hard decoding result; wherein the hard decoding result comprises first suggested values of component codes of at least one dimension of the multiple dimensions; (c) performing at least one additional read attempt of the group of flash memory cells to provide additional data; (d) performing a partial extensiveness soft decoding the additional data, in response to the first suggested values, to provide a soft decoding result; and (e) wherein the soft decoding result comprises second suggested values of component codes of one or more dimensions of the multiple dimensions.

Fast decoding of data stored in a flash memory

A method for managing an encoding process, the method includes receiving or determining, by a processor, (i) code rates for multiple pages, and (ii) sizes of a plurality of data segments to be stored in the multiple pages after being encoded to provide multiple codewords; determining, by the processor, sizes of the multiple codewords while maintaining the code rates for the multiple pages and minimizing a number of split data segments out of the plurality of data segments, wherein each split data segment is split between at least two codewords of the multiple codewords, wherein a retrieval of the split data segment involves a retrieval of the at least two codewords; and sending to an encoder information about the sizes of the multiple codewords.

Codeword management

A method of managing a non-volatile memory module, the method may include: allocating, by a memory controller, logically erased physical blocks of a non-volatile memory module to a spare block pool; allocating, by the memory controller, physical blocks from the spare block pool to become buffer blocks of a buffer of the non-volatile memory module; and controlling, by the memory controller, a utilization of the buffer blocks of the buffer by applying a page based buffer management scheme.

Advanced management of a non-volatile memory

A method for using a single spare block pool in flash memory comprising: allocating a plurality of flash memory arrays, wherein each flash memory array comprises a plurality of flash memory blocks; within a main flash memory array: allocating a used block pool comprising a plurality of used blocks and allocating a main spare block pool comprising a plurality of spare blocks; within each of the other flash memory arrays: allocating a used block pool comprising multiple used blocks; allocating a minimum spare block pool comprising a minimum number of spare blocks; allocating the main spare block pool and each of the minimum spare block pools to a single spare block pool; transferring a spare block from the main spare block pool to one of the minimum spare block pools; and transferring a spare block from a first minimum spare block pool to a second minimum spare block pool.

System and method for allocating and using spare blocks in a flash memory

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Netanya, Israel

Avigdor Segal