Gsi Technology, Inc.

Neomagic Israel Ltd.

Zikbit Ltd.

Mikamonu Group Ltd.

Associative Computing, Inc.

Gsi Technology Israel Ltd.

Avidan Akerib

Eli Ehrman

Oren Agam

Moshe Meyassed

Lee-Lean Shu

Chao-Hung Chang

Pat Lasserre

LeeLean Shu

Elona Erez

Josh Meir

Yoav Lavi

Moshe Lazer

Yair Alpern

Dan Ilan

Joseph Shain

Yaron Serfati

Ronen Stilkol

Mark Wright

Nitin Gupta

Nitish Arya

Michael Mordison

Adi Bar-Lev

An associative graph search system includes a KNN graph determiner to determine in advance W neighbors of each item in a dataset and to store each item and its neighbors in a KNN graph, a reduced dimension vector finder implemented on an associative processing unit (APU) to find a first number of first nearest neighbors of a query vector, the APU operating in a constant complexity irrespective of the size of the number, a result expander to find for each first nearest neighbor, W second nearest neighbors using the KNN graph thereby creating a group of neighbors, and a KNN full dimension vector re-ranker to find a final number of full dimension nearest neighbors of the full dimension query vector from the group of neighbors.

Associative graph search

A unit for accumulating a plurality of multiplied bit values includes a first row and a second row of input units, a bit-wise multiplier and a bit-wise accumulator. The first row receives a pipeline of the bits of a multiplicand A and the second row, to the left of the first row, receives a pipeline of the bits of a multiplicand B. The bit-wise multiplier, below the first row of input units, includes multiplier bit-line processors formed into rows and columns. Some rows of the bit-wise multiplier bit-wise multiplies bits of a current multiplicand A with one bit of a current multiplicand B and some rows of the bit-wise multiplier handle sum and carry values between the bits. The bit-wise accumulator, to the right of the bit-wise multiplier, includes a column of accumulator bit-line processors. Each accumulator bit-line processor accumulates output of a row of the bit-wise multiplier.

Pipeline architecture for bitwise multiplier-accumulator (MAC)

A system including a secure, in-memory unit implemented on an associative processing unit (APU), for creating encrypted vectors. The in-memory unit includes a data store and an encryptor. The data store stores data and the encryptor encrypts the data into an encrypted vector. Optionally, the unit includes a neural proxy hash encoder that encodes the data into an encoded vector, and, in this embodiment, the encryptor encrypts the encoded vector into an encrypted encoded vector. The neural proxy hash encoder includes a trained neural network which includes a plurality of layers that encode the data into feature sets. The trained neural network encodes image files, audio files, or large data sets. The APU is implemented on SRAM, non-volatile, or non-destructive memory.

Secure in-memory units for transmitting and receiving encoded vectors for external secure similarity searches

A system for natural language processing includes a memory array and a processor. The memory array is divided into a similarity section storing a plurality of feature vectors, a SoftMax section in which to determine probabilities of occurrence of the feature vectors, a value section storing a plurality of modified feature vectors, and a marker section. The processor activates the array to perform parallel operations in each column indicated by the marker section: a similarity operation in the similarity section between a vector question and feature vectors stored in indicated columns; a SoftMax operation in the SoftMax section to determine an associated SoftMax probability value for indicated feature vectors; a multiplication operation in the value section to multiply the associated SoftMax value by modified feature vectors stored in indicated columns; and a vector sum in the value section to accumulate an attention vector of output of the multiplication operation.

Natural language processing with k-NN

A system for detecting changes between two temporally different images includes an image divider, a Convolutional Neural Network (CNN) feature encoder, an image alignment system, a feature comparator, a CNN feature decoder and segmenter, and a block combiner. The image divider divides a first and second image into a plurality of image blocks. CNN feature encoder encodes the image blocks from the first and second image into first and second feature sets respectively. The image alignment system aligns the first and second image by searching for matching anchor vectors in the first and second feature sets using a similarity search. The feature comparator produces change feature sets from the first and second feature sets of the aligned image blocks, and the CNN feature decoder and segmenter creates segmented change image blocks from the change feature sets. The block combiner combines segmented change image blocks into a segmented change image.

Satellite imagery

A deduplication system includes a similarity searcher, a difference calculator, and a storage manager. The similarity searcher searches for a similar fingerprint in a database storing a plurality of local sensitive fingerprints, resembling a new fingerprint of a new block. The difference calculator computes a difference block between the input block and a similar block associated with the found similar fingerprint, and the storage manager updates the database with the new fingerprint and stores the difference block, if not empty, in a store. A method for deduplication includes searching in a database, storing a plurality of local sensitive fingerprints, a similar fingerprint, resembling a new fingerprint of a new block, calculating a difference block between the input block and a similar block associated with the similar fingerprint, if found, updating the database with the new fingerprint and storing the difference block, if it is not empty, in a storage unit.

Deduplication of data via associative similarity search

A memory device includes a plurality of memory units and a global responder (RSP) unit. Each memory unit includes a memory array of memory cells arranged in rows and columns, and an RSP unit. The memory array receives horizontal input data rotated for storage as data candidates in columns of the array. At least one of the rows is a calculation row receiving per-bit-line Boolean AND operations between bits of a marker row and bits of a row of data of the data candidates. The RSP unit includes wired-OR circuitry operative on the calculation row to generate a responder signal indicating whether there is one cell in the calculation row having a predefined value identifying a data candidate in the memory array. The global RSP unit receives multiple responder signals, one from at least two of the RSP units, and performs Boolean OR operations on the multiple responder signals.

Global responder signal circuitry for memory arrays

A method for random data distribution in a memory array from a source row to a destination row includes receiving a plurality of pairs of addresses, where each pair includes a source address of a source cell in the source row and a destination addresses of a destination cell in a destination row, storing the source address in cells of a column associated with the destination cell, creating a Boolean algebra expression defining a correlation between each one of the source addresses and a value stored in each one of the source cells, where applying the Boolean algebra expression on any one of the source addresses provides a value of one of the source cells, concurrently applying the Boolean algebra expression on a plurality of columns storing the source addresses and concurrently writing a plurality of results on the destination row.

System and method for random data distribution in a memory array

A device for in memory vector-matrix multiplication includes a memory array and in-memory logic. The memory array has at least two sections and stores a multiplier matrix. The memory array also receives and stores an input multiplicand arranged in a vector such that the operands of the vector-matrix multiplication are located on a same column of the memory array. Each of the sections is one of: a volatile memory array, a non-volatile memory array, a destructive memory array and a non-destructive memory array. The in-memory logic computes an output of the vector-matrix multiplication using the stored input vector and the stored multiplier matrix. The memory array is one of the following type of memory array: RAM, DRAM, SRAM, Re-RAM, ZRAM, MRAM and Memristor.

In memory matrix multiplication and its usage in neural networks

A cascading search system includes an associative memory array, a similarity match processor and an exact match processor. The columns of the array store a plurality of multiportion data vectors and have a first section, for a first portion of a vector, a second section for storing a second portion of a vector and a match row. The similarity match processor performs a parallel similarity search of a similarity query in the first sections and stores a match bit indication in the match row of the column. Each match bit indication indicates if its column has a first portion which matches the similarity query. The exact match processor performs an exact search in parallel in the second section of each similarity matched column whose match bit indication indicates a match of its first section and outputs those similarity matched columns whose second portions match the exact query.

In-memory efficient multistep search

A unit for accumulating a plurality N of multiplied M bit values includes a receiving unit, a bit-wise multiplier and a bit-wise accumulator. The receiving unit receives a pipeline of multiplicands A and B such that, at each cycle, a new set of multiplicands is received. The bit-wise multiplier bit-wise multiplies bits of a current multiplicand A with bits of a current multiplicand B and to sum and carry between bit-wise multipliers. The bit-wise accumulator accumulates output of the bit-wise multiplier thereby to accumulate the multiplicands during the pipelining process.

A method for in memory computation of a neural network, the neural network having weights arranged in a matrix, includes previously storing the matrix in an associated memory device, receiving an input arranged in a vector and storing it in the memory device, and in-memory, computing an output of the network using the input and the weights.

A method to determine an extreme value of a plurality of data candidates includes storing each data candidate of a plurality of data candidates in a separate column of an associative memory, initializing a row of marker bits by setting each marker bit to a value of 1, computing a subsequent row of marker bits by performing in parallel a Boolean AND operation between a previous row of marker bits and a row of bits of the data candidates, starting with the row of most significant bits of the data candidates, performing a Boolean OR operation between the marker bits in the subsequent row of marker bits to generate a subsequent RSP value, identifying the extreme value from among the plurality of data candidates when there is only one marker bit having a value of 1 in the subsequent row of marker bits coinciding with when said subsequent RSP value is a 1, and if the identifying is false, repeating the computing on a row of next most significant bits, performing and identifying until the identifying is true.

Memory device for determining an extreme value

A non-destructive memory array implements a full adder. The array includes a column connected by a bit line and a full adder unit. The column stores a first bit in a first row of the bit line, a second bit in a second row of the bit line, and an inverse of a carry-in bit in a third row of the bit line. The full adder unit stores, in the second and third rows of the bit line, a sum bit and a carry out bit output, respectively, of adding the first bit, the second bit and the carry-in bit. The full adder unit does not overwrite any of the bits when a full adder table indicates that the sum bit and the carry out bit are equivalent to the second bit and the carry-in bit.

In-memory full adder

A system for performing cascading search includes an associative memory array, a controller, a similarity search processor and an exact match processor. The associative memory array stores a plurality of multiportion data vectors stored in at least one column of the associative memory array. Each vector has a first portion and a second portion which are aligned to each other in the column. The controller controls the associative memory array to perform a similarity search of a similarity query on the first portion and an exact search of an exact query on the second portion. The similarity match processor generates a match row including match bit indications aligned with each similarity matched column. The match row indicates which columns have first portions which match to the similarity query. The exact match processor outputs exact match columns from among the similarity matched columns which have second portions which match the exact query.

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Tel Aviv, Israel

Avidan Akerib