Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Avichay Haim Hodes

Yehuda Hahn

Shay Benisty

Alexander Bazarsky

Karin Inbar

Michael James

Nir Amir

Yuval Bahar

Alex Mostovoy

Rajeev Nagabhirava

Alex Bazarsky

Vered Kelner

Einat Lev

Oren Shmuel Cohen

Guy Freikorn

Detecting the removal of a data storage device from a storage system involves first determining that a shorter pin of an electrical connector of a storage device is disconnected from a mating electrical connector, such as by sensing a voltage drop on that pin, then determining at a later time that a longer pin of the connector is disconnected from the mating connector. Responsive to determining that the longer pin was disconnected after a predetermined period of time after the shorter pin, a conclusion may be made that the storage device has been removed from the system as opposed to being subject to a simple device power aberration. Thus, responsive data destruction action(s) may be taken to render the data stored on the device inaccessible to the attacker thereby protecting the device even after the device is removed from the storage system.

Detection of data storage device removal

A method of forming a semiconductor device includes through-package debug features enabling debug of a BGA package while mounted to a printed circuit board or other host device. In one example, the through-package debug features are filled or plated vias extending from a surface of the semiconductor device, through a device housing, down to test pads on the substrate. In another example, the through-package debug features are open channels formed from a surface of the semiconductor device.

Semiconductor device including through-package debug features

A data storage device and method for enhanced recovery through data storage device discrete-component-hardware-reset are provided. In one embodiment, the data storage device determines that a subset of a plurality of memory dies is non-responsive, sends a request to a host to accept longer delays associated with the subset of the plurality of memory dies, power-cycles the subset of the plurality of memory dies, and then informs the host that the latency associated with those dies has been restored to normal latency or that the subset of the plurality of memory dies are inactive (in case of unsuccessful recovery). Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Data storage device and method for enhanced recovery through a hardware reset of one of its discrete components

A storage system includes one or more data storage devices, a PCIe switch coupled to the one or more data storage devices, and a controller unit coupled to the PCIe switch. The one or more data storage devices are DRAM-less. The controller unit includes a dynamic random access memory (DRAM) host memory buffer (HMB) controller and a DRAM pool or a controller memory buffer (CMB) controller, a root complex/port, and the DRAM pool. The DRAM pool includes one or more DRAM devices. The one or more data storage devices are configured to interact with the controller unit and store data to a DRAM of the DRAM pool of the controller unit.

Enterprise host memory buffer for DRAM-less SSD

A storage system includes two or more data storage devices and a controller coupled to the two or more data storage devices. Each data storage device of the two or more data storage devices includes zoned namespace (ZNS) architecture. The controller is configured to collect thermal statistics for each data storage device of the two or more data storage devices, analyze the collected thermal statistics, and designate a zone by selecting one or more dies within at least one data storage device of the two or more data storage devices based on the analyzed collected thermal statistics. The data storage device includes a memory device having a plurality of dies and a controller coupled to the memory device. The controller is configured to collect thermal statistics for each die of the plurality of dies, analyze the collected statistics, and allocate one or more dies to form a zone.

Controlled system management based on storage device thermal load

Embodiments of the present disclosure generally relate to storage devices, such as SSDs. A data storage device comprises an encrypted interface, one or more flash memory devices, and a controller configured to receive one or more workloads of data through the encrypted interface. Upon a threshold being met, the controller performs a diagnosis of one or more operating parameters of the one or more workloads of data. Based on the diagnosis, the data storage device is optimized by recalibrating one or more of: a partitioning of bits per cell of the one or more flash memory devices, one or more flash management parameters of the data storage device, and a programming rate of the storage device.

Adjustment of storage device parameters based on workload characteristics

A storage system includes one or more data storage devices, a PCIe switch coupled to the one or more data storage devices, and a controller unit coupled to the PCIe switch. The controller unit includes a dynamic random access memory (DRAM) host memory buffer (HMB) controller and a DRAM pool or a controller memory buffer (CMB) controller, a root complex/port, and the DRAM pool. The DRAM pool includes one or more DRAM devices. The one or more data storage devices are configured to interact with the controller unit and store data to a DRAM of the DRAM pool of the controller unit.

Enterprise host memory buffer

The present disclosure generally relates to utilizing a port scheduler within a data storage device controller to schedule data transfers and determine which port should be utilized for each data packet transferred. The data storage device comprises a multi-port system on a host interface. The port scheduler can consider the following factors for example: link workload, idle time for each port, link power state, throughput for each port, speed of each link, priority of data transfer, and quality of service (QoS). Based upon an analysis of one or more of the factors, the port scheduler can transfer data on a port that is not associated with the data to ensure efficient multi-port usage.

Dynamic port allocation in PCIe bifurcation system

A method and apparatus for enhancing reliability of a data storage device. The storage device controller is configured to convert a typical UBER-type event to an MTBF (FFR) event by converting a data error event into a drive functional failure. In this context, the converted error is not counted as an UBER type event for purposes of determining the reliability of the storage device.

Methods and apparatus for enhancing uber rate for storage devices

The present disclosure generally relates to power management for an external storage device. The external storage device includes a power allocation unit coupled to an array of memory devices. A single bridge is present to provide a connection to a host device. The memory devices have operational power states that utilize a first amount of power and non-operational power states that utilize a second amount of power that is less than the first amount of power. The power allocation unit changes the power state of the individual memory devices between operational and non-operational based upon need, but also ensures that the external storage device does not exceed the total power allocation. Thus, the power allocation unit may change a power state of one memory device from operational to non-operational in order to change the power state of another memory device from non-operational to operational.

Power allocation management for external storage

A semiconductor device includes through-package debug features enabling debug of a BGA package while mounted to a printed circuit board or other host device. In one example, the through-package debug features are filled or plated vias extending from a surface of the semiconductor device, through a device housing, down to test pads on the substrate. In another example, the through-package debug features are open channels formed from a surface of the semiconductor device.

The present disclosure generally relates to a method and device for reduce the amount of energy used to revert data within a storage device to a consistent state after a power loss event. Once power is lost from a host device, and prior to complete shutdown, a log is created within non-volatile memory (NVM) of the storage device. The log contains logical block addresses (LBAs) corresponding to data that experienced a write failure. At the next power-on event, the log is checked to see if any LBAs are present. If LBAs are present in the log, then the data that experienced a write failure can be properly written to the storage device.

Delayed write failure logging

A solid state device is disclosed comprising an array of memory units, an interface connected to the memory units, at least one arrangement to monitor a temperature of the solid state device and an arrangement to monitor low power mode statistics of the solid state device and compare the low power mode statistics to a critical usage point power threshold at a temperature measured, wherein the arrangement to monitor the low power mode statistics of the solid state device is further configured to change a power mode of the solid state device based upon the low power mode statistics.

Energy optimized power state declarations for solid state drives

Aspects of the present disclosure provide various apparatus, devices, systems and methods for dynamically configuring a cache partition in a solid state drive (SSD). The SSD may include non-volatile memory (NVM) that can be configured to store a different number of bits per cell. The NVM is partitioned into a cache partition and a storage partition, and the respective sizes of the partitions is dynamically changed based on a locality of data (LOD) of the access pattern of the NVM.

Growing community of inventors

Kfar Ben-Nun, Israel

Avichay Haim Hodes