Tower Semiconductor Ltd.

Samsung Electronics Co., Ltd.

Hillberry Gat Ltd.

Avi Strum

Yakov Roizin

Amos Fenigstein

Assaf Lahav

Doron Pardess

Alexey Heiman

Viktor Goldovsky

Alexei Heiman

David Avner

Yohanan Davidovich

A method for manufacturing an optical system, the method includes obtaining an intermediate semiconductor item that comprises a silicon substrate and a stack of layers that comprises a monocrystalline silicon layer and is positioned between two silicon alloy layers; wherein the silicon substrate comprises diffusion regions; and performing Complementary Metal-Oxide-Semiconductor (CMOS) compliant operations to provide, based on the intermediate semiconductor item, a first switching cell that is formed on the silicon substrate.

Method for manufacturing an optical switching system

An optical switching system, including a silicon substrate; a first switching cell that is formed on the silicon substrate, wherein the first switching cell includes first till thirs ports, a monocrystalline silicon waveguide (MSW) that comprises a first MSW segment and a second MSW segment; and an actuation unit that is configured to move each one of the first MSW segment and the second MSW segment between at least three different positions thereby determining whether an optical signal received at the first port is (a) directed through the MSW to the second port, or (b) is directed to the third port through a first bus waveguide.

Optical switching system

An image sensor module that comprises a die, wherein the die comprises light sensors and optics; and wherein the optics comprises luminescent elements that represent die manufacturing information that is indicative of a manufacturing process of the die.

Image sensor module and a method for evaluating an image sensor

A global shutter image sensor formed on an n-type bulk substrate and including pixels having pinned n-type photodiodes and memory nodes formed in designated n-doped epitaxial layer regions that are separated from the bulk substrate by a p-type vertical (potential) barrier implant. Each memory node includes both a buried channel portion and a contiguous pinned diode portion having different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion during global charge transfer from an adjacent photodiode. The p-type vertical (potential) barrier implant is coupled to ground, and the bulk substrate is switched between a low integration voltage level during integration periods, and a high reset voltage level, whereby the photodiodes are globally reset without requiring reset transistors. P-type sinker implant sections and p-type vertical barrier implants form box-like diffusions around each pixel's photodiode and memory node.

Image sensor pixel with memory node having buried channel and diode portions formed on N-type substrate

A global shutter (GS) image sensor pixel includes a pinned photodiode connected to a memory node by a first transfer gate transistor, and a floating diffusion connected to the memory node by a second transfer gate transistor. The memory node includes a buried channel portion disposed under the first transfer gate transistor and a contiguous pinned diode portion disposed between the first and second transfer gate transistors, where the two memory node portions have different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion. The floating diffusion node similarly includes a buried channel portion disposed under the second transfer gate transistor and a contiguous pinned diode portion that generate a second intrinsic lateral electrical field that drives electrons into the pinned diode portion of the floating diffusion. A 6T CMOS pixel is disclosed that facilitates low-noise CDS readout.

Image sensor pixel with memory node having buried channel and diode portions

A method for fabricating image sensors and other semiconductor ICs that controls the amount of hydrogen generated during back-end processing. The back-end processing includes forming multiple metallization layers after front-end processing is completed (i.e., after forming the pre-metal dielectric), where each metallization layer includes a patterned aluminum structure, an interlevel dielectric (ILD) layer including TEOS-based oxide formed over the patterned aluminum structure. A cap layer including a low-moisture content oxide such as silane oxide (i.e., SiOgenerated by way of a silane CVD process) is formed over at least one ILD layer. The cap layer serves as an etch-stop for the subsequently-formed metal layer of a next metallization layer by isolating the underlying ILD material from the plasma environment during aluminum over-etch, which significantly reduces the production and migration of hydrogen into front-end structures.

Back-end processing using low-moisture content oxide cap layer

A match-in-place-type compare operation utilizes a string of Magnetic Tunnel Junction (MTJ) elements including storage layers and sense layers having different anti-ferromagnetic structures respectively having higher and lower blocking temperatures. Confidential data is written into the storage layers of the MTJ elements by heating the elements above the higher blocking temperature, and then orienting the storage and sense layers in first storage magnetization directions using field lines. The elements are then cooled to an intermediate temperature between the higher and lower blocking temperatures, and the field lines are turned off, setting the sense layers to preliminary storage magnetization directions opposite to the first directions. During a pre-compare phase, an input logic pattern is written into the sense layers by heating to the intermediate temperature. During a compare operation, with the field lines turned off, resistance of the MTJ string is detected by passing a read current through the string.

High-speed compare operation using magnetic tunnel junction elements including two different anti-ferromagnetic layers

A logic unit for security engines or content addressable memory including Magnetic Tunnel Junction (MTJ) elements connected in series to form a NAND-type string, where each MTJ element includes a storage layer and a sense layer having different anti-ferromagnetic materials respectively having higher and lower blocking temperatures. During write/program, the string is heated above the higher blocking temperature, and magnetic fields are used to store bit values of a confidential logical pattern in the storage layers. The string is then cooled to an intermediate temperature between the higher and lower blocking temperatures and the field lines turned off to store bit-bar (opposite) values in the sense layers. During a pre-compare operation, the MTJ elements are heated to the intermediate temperature, and an input logical pattern is stored in the sense layers. During a compare operation, with the field lines off, a read current is passed through the string and measured.

Logic unit including magnetic tunnel junction elements having two different anti-ferromagnetic layers

A three-dimensional (3D) non-volatile memory (NVM) array including spaced-apart horizontally-disposed bitline structures arranged in vertical stacks, each bitline structures including a mono-crystalline silicon beam and a charge storage layer entirely surrounding the beam. Vertically-oriented wordline structures are disposed next to the stacks such that each wordline structure contacts corresponding portions of the charge storage layers. NVM memory cells are formed at each bitline/wordline intersection, with corresponding portions of each bitline structure forming each cell's channel region. The bitline structures are separated by air gaps, and each charge storage layer includes a high-quality thermal oxide layer that entirely covers (i.e., is formed on the upper, lower and opposing side surfaces of) each of the mono-crystalline silicon beams. The 3D NVM array effectively includes multiple NVM NAND string structures, where each NAND string structure is formed by multiple series-connected NVM memory cells disposed along an associated bitline structure.

Three-dimensional NAND memory with stacked mono-crystalline channels

An X-ray image sensor having scintillating material embedded into wave-guide structures fabricated in a CMOS image sensor (CIS). After the CIS has been fabricated, openings (deep pores) are formed in the back side of the CIS wafer. These openings terminate at a distance of about 1 to 5 microns below the upper silicon surface of the wafer. The depth of these openings can be controlled by stopping on a buried insulating layer, or by stopping on an epitaxial silicon layer having a distinctive doping concentration. The openings are aligned with corresponding photodiodes of the CIS. The openings may have a shape that narrows as approaching the photodiodes. A thin layer of a reflective material may be formed on the sidewalls of the openings, thereby improving the efficiency of the resulting waveguide structures. Scintillating material (e.g., CsI(Tl)) is introduced into the openings using a ForceFill&#x2122; technology or by mechanical pressing.

High-resolution integrated X-ray CMOS image sensor

A method for generating three-dimensional (3D) non-volatile memory (NVM) arrays includes forming multiple parallel horizontally-disposed mono-crystalline silicon beams that are spaced apart and arranged in a vertical stack (e.g., such that an elongated horizontal air gap is defined between each adjacent beam in the stack), forming separate charge storage layers on each of the mono-crystalline silicon beams such that each charge storage layer includes a high-quality thermal oxide layer that entirely covers (i.e., is formed on the upper, lower and opposing side surfaces of) each of the mono-crystalline silicon beams, and then forming multiple vertically-disposed poly-crystalline silicon wordline structures next to the stack such that each wordline structure is connected to each of the bitline structures in the stack by way of corresponding portions of the separate charge storage layers. The memory cells are accessed during read/write operations by way of the corresponding wordline and bitline structures.

Method for generating a three-dimensional NAND memory with mono-crystalline channels using sacrificial material

An imaging device module includes a circuit mounting layer; a bottom glass layer disposed above the circuit mounting layer; a silicon die disposed above the bottom glass layer; a top glass layer disposed above the silicon layer; and a lens holder disposed above the top glass layer. The silicon die includes an image sensor. The lens holder contains an optical component.

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Haifa, Israel

Avi Strum