Motorola Corporation

Freescale Semiconductor,inc.

Avi Shalev

Avi Hagai

Eliezer Weitz

Moti Kurnick

Yoram Yeivin

Adi Katz

Avraham Ganor

Vadim Vayzer

Yossi Socoletzki

A communication controller ( ) for handling and processing data packets received from a large number of communication channels ( ). The communication controller ( ) comprising of: a processor ( ) for processing data; a serial interface ( ), coupled to the communication channels ( ). A multi channel controller ( &prime;) coupled to the serial interface ( ) and the processor ( ), for interfacing between the communication channels ( ) and the processor ( ). The communication channels ( ) and the serial interface ( ) send and receive data packets. The processor ( ) sends, receives and processes data words. The multi channel controller ( ) receives data packets from the serial interface ( ), concatenates data packets and sends data words to the processor ( ). The multi channel controller ( ) receives data words from the processor ( ), and transmits data packets to the serial interface ( ).

Multi channel controller

A communication system ( ) has a first processor ( ) and a second processor ( ). The first processor ( ) has a first number of address bits (e.g., A&equals;5) to select a first device ( ), and the second processor ( ) has a second number of address bits (e.g., B&equals;4 to select a second device ( ). The processors ( ) are coupled to the devices ( ) by a shared bus ( ) with a total number of bit lines ( ) which is smaller than or equal to the sum of the first and second numbers of bits (e.g., N&equals;8). The bit lines ( ) are assigned to a first outer set ( ), a second outer set ( ) and to an inner set ( ). LSB-bits from the first processor ( ) are coupled to the first outer set ( ), LSB-bits from the second processor ( ) are coupled to the second outer set ( ), and MSB-bit of first and second processors ( ) are multiplexed to the lines of the inner set ( ).

Communication system with communication controller and multiple physical interfaces, and method

A communication controller for handling high speed multi protocol data streams, wherein a stream is comprised of frames. Communication controller has two processors, second processor initializes first processor and handles high level management and protocol functions, first processor handles the data stream transactions. First processor and second processors are coupled to a two external buses. First processor handles a transactions of a frame by executing a task. First processor performs a task switch when there is a need to fetch information from an external unit, coupled to either first or second external bus, if it did process a whole frame, or if there is a need to fetch a portion of a frame from a communication channel.

High performance communication controller for processing high speed data streams wherein execution of a task can be skipped if it involves fetching information from external memory bank

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Tel Aviv, Israel

Avi Shalev