Tower Semiconductor Ltd.

Matsushita Electric Industrial Co., Ltd.

Avi Parvin

Noam Eshel

Yasuhiro Tomita

Roda Kanawati

Hitoshi Suwa

Manabu Komiya

Jeffrey Allan Jacob

Allon Parag

Tamas Toth

Efraim Aharoni

Einat Arad Ophir

For example, a multi voltage-domain Electro Static Discharge (ESD) power clamp may include a plurality of pins; and an ESD array including a cascaded plurality of ESD power clamps. For example, the ESD array may include a plurality of ESD array portions configured to protect a respective plurality of voltage domains from ESD. For example, the ESD array may be configured to connect the plurality of ESD array portions between a respective plurality of pin pairs from the plurality of pins. For example, an ESD array portion corresponding to a voltage domain may include one or more ESD power clamps of the cascaded plurality of ESD power clamps. For example, the ESD array portion may be configured to protect a voltage range of the voltage domain.

Multi voltage-domain electro static discharge (ESD) power clamp

In conventional memory arrays in which a bit line is shared by memory cells, a cell current flows over into neighbor cell(s) in a program verify process, and therefore, the threshold of a memory cell to be programmed is erroneously determined to be lower. Therefore, in a program verify process, a control circuitwrites a fail value to a neighbor cell bufferwhen all neighbor cell(s) having an offset of n or less from a memory cell to be programmed are in the erased state, and when otherwise, writes a pass value to the neighbor cell buffer. The control circuitverifies input write data and also verifies data stored in the neighbor cell buffer(s). In the latter verify process, a verify voltage higher than an ordinary one is used to compensate for the leakage of cell current.

Flash memory and program verify method for flash memory

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Netanya, Israel

Avi Parvin