Intel Corporation

National Semiconductor Corporation

Technion Research & Development Foundation Limited

Avi Mendelson

Eliezer Weissmann

Bratin Saha

Hu Tiger Chen

Shoumeng Yan

Mohan Rajagopalan

Peinan Zhang

Debendra Das Sharma

David J Harriman

Robert G Blankenship

Mahesh U Wagh

Mark B Rosenbluth

Jasmin Ajanovic

Scott Dion Rodgers

Ohad Falik

Anil Vasudevan

Prashant Sethi

Ilan Pardo

Sridhar Muthrasanallur

Ajay V Bhatt

James E Akiyama

Eran Tamari

Ying Gao

Doron Shamia

Peter J Barry

Ronny Ronen

Xiaocheng Zhou

Jesse Z Fang

Zhou Xiaocheng

Michael Mishaeli

Lev Finkelstein

Aviad Cohen

Dmitry Rudoy

Efraim Rotem

Hong Wang

Alon Naveh

Gad Shlomo Sheaffer

Boris Ginzburg

Ron Gabor

Guy M Therien

David A Koufaty

Ganapati Srinivasa

Anil Aggarwal

Julius Yuli Mandelblat

Scott D Hahn

Yuval Yosef

Uri C Weiser

Baruch Solomon

Jonathan Levy

Freddy Gabbay

Danny Hendler

Gao Ying

Hu Chen

In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.

Migrating tasks between asymmetric computing elements of a multi-core processor

Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

Shared virtual memory

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Atomic operations in PCI express

Transaction layer packet formatting

PCI express transaction descriptor

Transaction re-ordering

Prefectching in PCI express

Disclosed are embodiments of a system, methods and mechanism for using idle thread units to perform acceleration threads that are transparent to the operating system. When the operating system scheduler has no work to schedule on the idle thread units, the operating system may issue a halt or monitor/mwait or other instruction to place the thread unit into an idle state. While the thread unit is idle, from the operating system perspective, the thread unit may be utilized to perform speculative acceleration threads in order to accelerate threads running on non-idle thread units. The context of the idle thread unit is saved prior to execution of the acceleration thread and is restored when the operating system requires use of the thread unit. The acceleration threads are transparent to the operating system. Other embodiments are also described and claimed.

Acceleration threads on idle OS-visible thread execution units

Embodiments of the invention provide language support for CPU-GPU platforms. In one embodiment, code can be flexibly executed on both the CPU and GPU. CPU code can offload a kernel to the GPU. That kernel may in turn call preexisting libraries on the CPU, or make other calls into CPU functions. This allows an application to be built without requiring the entire call chain to be recompiled. Additionally, in one embodiment data may be shared seamlessly between CPU and GPU. This includes sharing objects that may have virtual functions. Embodiments thus ensure the right virtual function gets invoked on the CPU or the GPU if a virtual function is called by either the CPU or GPU.

Language level support for shared virtual memory

Methods, apparatus, and articles of manufacture control a device or system that has an operational limit related to the rate or frequency of operation. The frequency of operation is controlled at a variable rate calculated to maximize the system or apparatus performance over a calculated period of time short enough that a controlling factor, such as power consumption, does not vary significantly during the period. Known system parameters, such as thermal resistance and capacitance of an integrated circuit (IC) and its package, and measured values, such as current junction temperature in an IC, are used to calculate a time-dependent frequency of operation for the upcoming time period that results in the best overall performance without exceeding the operational limit, such as the junction temperature.

Methods and apparatus for optimal voltage and frequency control of thermally limited systems

In one embodiment, the present invention includes a method including initiating a cleaning operation to clear a first processor core of a system of pending operations, and preventing injection of new events into a second processor core if the cleaning operation is not serviced in the first processor core. In this way, lock situations may be broken without their detection. Other embodiments are described and claimed.

Breaking a lock situation in a processor without detection of the lock situation using a multi-level approach

Growing community of inventors

Haifa, Israel

Avi Mendelson