Marvell Asia Pte., Ltd.

Marvell Israel (Misl) Ltd.

Avi Haimzon

Noam Mizrahi

Timor Kardashov

Adi Katz

Ruven Torok

A first solid state drive (SSD) includes a built-in network interface device configured to communicate via a network fabric, and a second SSD includes a built-in network interface device configured to communicate via the network fabric. A connection is opened between the first SSD and the second SSD over the network fabric, where the first SSD is further communicatively coupled to the second SSD further over an interconnect associated with a host computer. The first SSD encapsulates a non-volatile memory over fabric (NVMe-oF) command to transfer data between the first SSD and the second SSD in a capsule and sends the capsule to the second SSD over the connection. The second SSD executes the NVMe command to transfer the data between the first SSD and the second SSD over the connection according to an NVMe-oF communication protocol and without transferring any of the data to the host computer.

Transferring data between solid state drives (SSDs) via a connection between the SSDs

Methods and systems for collecting operational data from a target digital system are disclosed. In some embodiments, a method includes determining a test configuration to be used to configure a probe circuit. Determining the test configuration may include selecting one or more signal sources, defining one or more signal patterns within the selected signal sources, and defining one or more trigger events associated with the one or more signal patterns. Based on the test configuration, the probe circuit selects input/output (I/O) channels for a test cycle and captures one or more traces from the selected I/O channels during the test cycle.

Configurable integrated logic analyzer

A first solid state drive (SSD) includes a first built-in network interface device configured to communicate via a network fabric, and a second SSD includes a second built-in network interface device configured to communicate via the network fabric. A connection is opened between the first SSD and the second SSD over the network fabric. Based on a non-volatile memory over fabric (NVMe-oF) communication protocol, an NVMe command to transfer data between the first SSD and the second SSD over the connection is encapsulated in a capsule. The capsule is sent from the first SSD to the second SSD over the connection via the network fabric. The second SSD executes the NVMe command in the capsule to transfer the data between the first SSD and the second SSD over the connection.

A first master receives a first virtual address in a virtual memory, the first virtual address in the virtual memory corresponding, according to a mapping function, to a first physical address of a first physical memory bank which is to be accessed by the first master. The first master accesses the first physical address to perform a first memory operation in the first memory bank. A second master receives a second virtual address in a virtual memory, the second virtual address in the virtual memory corresponding, according to the mapping function, to a second physical address of a second physical memory bank which is to be accessed by the second master. Concurrently with access by the first master to the first physical address, the second master accesses the second physical address to perform a second memory operation in the second physical memory bank.

Accelerating access to memory banks in a data storage system

This disclosure can provide methods, apparatus, and systems for dividing an input clock or master clock by an integer or non-integer divisor and generating one or more balanced, i.e., 50% duty cycle, divided that are phase-aligned to the input clock. The non-integer divisors can include half-integers, N/2, e.g. the division can be denoted 2:N. The value of N for each phase-aligned, balanced, divided clock can be distinct. The method can include generating an input clock signal having an input clock frequency, generating a secondary clock signal that transitions between a first state and a second state based on the input clock signal, generating a delayed secondary clock signal that is time delayed relative to the secondary clock signal, and generating the output clock signal that has a frequency that is a non-integer division of the input clock frequency.

Growing community of inventors

Nes Ziona, Israel

Avi Haimzon