Optimaltest Ltd.

Optimal Plus Ltd.

Avi Golan

Gil Balog

Reed Linde

Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.

Systems and methods for test time outlier detection and correction in integrated circuit testing

Methods for slow test time detection of an integrated circuit during parallel testing

Parallel dies testing, mostly implemented on memory ICs&#x2014;Integrated Circuits, significantly reduced overall test time. In order to minimize the need for physical probing, wafer probe card technology to allow simultaneous probing, ATE&#x2014;Automated Test Equipment with enough channels and CPU power to handle the parallel testing. While new devices are designed with enough channels, and probe cards are designed and manufactured for each new device, the need to purchase new ATE to benefit from the technology is a heavy burden on parallel testing. It is proposed to interpose a multiplexer between the probe card and the ATE accompanied by a system that optimizes tester resources. The proposed system will allow test houses to benefit most from their investment without paying the full penalty of keeping less capable ATE.

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Tel Aviv, Israel

Avi Golan