International Business Machines Corporation

Avery Francois

Gregory William Alexander

Christian Jacobi

Robert J Sonnelitter, Iii

Ulrich Mayer

Ekaterina M Ambroladze

Jonathan T Hsieh

Kenneth Douglas Klapproth

Chad G Wilson

Ram Sai Manoj Bamdhamravuri

Richard Joseph Branciforte

Chunggeon Rhee

Anna Mozeshtam

Embodiments include processing commands on multiprocessor chip having a plurality of nodes that are interconnected via a clockwise ring network and a counterclockwise ring network. Aspects include receiving, by a first ring station associated with a first node of the plurality of nodes, the command for execution and transmitting, by the first ring station via one or more of the clockwise ring network and the counterclockwise ring network, the command for execution. Aspects also include receiving, by a second ring station associated with a second node of the plurality of nodes, the command for execution, wherein the second ring station is connected to a third ring station associated with a third node of the plurality of nodes via a first cross bar of the one or more cross bars and transmitting, by the second ring station to the third ring station via the first cross bar, the command for execution.

Bidirectional ring-based interconnection networks having a cross bar for multiprocessors

A computer system and a method implementing a remote access array are provided. A first drawer includes a first processor chip. A first main memory region is operatively connected to the first processor chip. A first non-addressable memory region is operatively connected to the first processor chip and includes the first remote access array. The first remote access array is configured to track data portions that are stored in the first main memory region and for which copies were created and sent to an external node. The first remote access array is backed up in the first main memory region. The first remote access array includes one or more entries and is configured to update all of the entries in response to a multi-drawer working partition being reduced to fit within the first drawer.

Remote access array

A computer data processing system includes an instruction pipeline having a front end and a back end, a decoding and dispatch unit to dispatch a current instruction; and a pipeline by-pass unit to invoke an out-of-order pipeline by-pass operation. The pipeline by-pass unit by-passes a section of the instruction pipeline such that the current instruction architecturally completes before initiating instruction execution. The computer data processing system further includes a post-completion execution unit that executes the current instruction after the current instruction architecturally completes.

Post completion execution in an out-of-order processor design

A computer-implemented method is provided and includes allocating, by a processor, an instruction to a first thread, decoding, by the processor, the instruction, determining, by the processor, a type of the instruction based on information obtained by decoding the instruction, and based on determining that the instruction is a disruptive complex instruction, changing a mode of allocating hardware resources to an instruction-based allocation mode. In the instruction-based allocation mode, the processor adjusts allocation of the hardware resources among a first thread and a second thread based on types of instructions allocated to the first and second threads.

Adjusting thread balancing in response to disruptive complex instruction

A method includes allocating a first entry in a global completion table (GCT) on a processor, responsive to a first instruction group being dispatched, where the first entry corresponds to the first instruction group. A data value applicable to the first instruction group is identified. An offset value applicable to the first instruction group is calculated by subtracting, from the data value, a base value previously written to a second entry of the GCT for a second instruction group. The offset value is written in the first entry of the GCT in lieu of the data value.

Offset-based mechanism for storage in global completion tables

Implementing processor instrumentation in a processor pipeline includes determining a pipeline depth of each micro-operator for an instruction group used in an execution phase of the processor pipeline. The pipeline depth corresponds with a duration of execution, each micro-operator performs a type of functional operation in the execution phase, and the instruction group includes all the micro-operators required for the execution phase. A targeted micro-operator is identified for which the processor instrumentation is being performed, and the pipeline depth corresponding with the targeted micro-operator is used to determine and report a performance of the targeted micro-operator as part of the processor instrumentation. Problems indicated by the processor instrumentation are diagnosed and addressed based on the performance of the targeted micro-operator.

Growing community of inventors

Austin, TX, United States of America

Avery Francois