Oracle International Corporation

Avadh P Patel

Jeffrey R Diamond

Ashok V Krishnamoorthy

Alan Paul Wood

Leick D Robinson

Priyank Faldu

A computer comprising one or more processors offering vector instructions may implement a direct convolution on a source data set. The source data set may be one-dimensional or multi-dimensional. For a given vector width, w, of the vector instructions, w consecutive data elements of the output data set are computed in parallel using vector instructions. For multi-dimensional data sets, multiple vectors of the output data set are computed for a single load of a set of vectors from the source data set. New vector instructions are disclosed to improve the performance of the convolution and to enable full utilization of the arithmetic logic units within the one or more processors.

Efficient direct convolution using SIMD instructions

A cache memory may be configured to store a plurality of lines, where each line includes data and metadata. A circuit may be configured to determine a respective number of edges associated with each vertex of a plurality of vertices included in a graph data structure, and sort the graph data structure using the respective number of edges. The circuit may be further configured to determine a reuse value for a particular vertex of the plurality of vertices using a respective address associated with the particular vertex in the sorted graph, and store data and metadata associated with the particular vertex in a particular line of the plurality of lines in the cache memory.

Cache memory architecture and policies for accelerating graph algorithms

A macro-switch is described. This macro-switch includes facing integrated circuits, one of which implements optical waveguides that convey optical signals, and the other which implements control logic, electrical switches and memory buffers at each of multiple switch sites. Moreover, the macro-switch has a fully connected topology between the switch sites. Furthermore, the memory buffers at each switch site provide packet buffering and congestion relief without causing undue scheduling/routing complexity. Consequently, the macro-switch can be scaled to an arbitrarily large switching matrix (i.e., an arbitrary number of switch sites and/or switching stages).

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Cedar Park, TX, United States of America

Avadh P Patel