Hrl Laboratories, LLC

Austin F Garrido

Peter Petre

Jose Cruz-Albrecht

Shankar R Rao

Adour Vahe Kabakian

Bryan H Fong

Gabriel L Virbila

Timothy J Derosier

Sanaz Adl

Described is a Neuromorphic Adaptive Core (NeurACore) cognitive signal processor (CSP) for wide instantaneous bandwidth denoising of noisy signals. The NeurACore CSP includes a NeurACore block, a globally learning layer, and a neural combiner. The NeurACore block is operable for receiving as an input a mixture of in-phase and quadrature (I/Q) signals and mapping the I/Q signals onto a neural network to determine complex-valued output weights of neural states of the neural network. The global learning layer is operable for adapting the complex-valued output weights to predict a most likely next value of the input I/Q signal. Further, the neural combiner is operable for combining a set of delayed neural state vectors with the weights of the global learning layer to compute an output signal, the output signal being separate in-phase and quadrature signals.

Low size, weight and power (swap) efficient hardware implementation of a wide instantaneous bandwidth neuromorphic adaptive core (NeurACore)

A system for real time bilinear interpolation includes a bilinear interpolation module capable of: generating pixel addresses for original image pixels of an original image needed for performing bilinear interpolation of the original image to form a resized image, wherein the generated pixel addresses assume all the original image pixels of the original image are accessible, and performing bilinear interpolation, and a pixel smart memory module capable: of sequentially receiving original image pixel rows of the original image an original image pixel row a time, predicting which original image pixel rows are needed for performing bilinear interpolation, storing only the needed sequentially received original image pixel rows in a memory, decoding the generated pixel addresses to form decoded addresses to access the needed original image pixel rows stored in the memory, and sending the needed original image pixel rows to the bilinear interpolation module for performing bilinear interpolation.

Efficient hardware design and implementation of image interpolation and resizing for image processing pipeline

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Northridge, CA, United States of America

Austin F Garrido