Advanced Micro Devices Corporation

Magnachip Semiconductor, Inc.

Hyundai Electronics America, Inc.

Austen John Hypher

Richard W Reeves

Gerald Robert Talbot

Warren Anderson

Shyam Sivakumar

Gerry Talbot

Gerry R Talbot

Matthew Scheffer

David John Workman

A termination impedance apparatus includes a variable pull-up resistor, a variable pull-down resistor, and a small-signal calibration circuit. The variable pull-up resistor is coupled between a first power supply voltage terminal and an output terminal. The variable pull-down resistor is coupled between the output terminal and a second power supply voltage terminal. The small-signal calibration circuit is for calibrating the variable pull-up resistor and the variable pull-down resistor to achieve a desired small-signal impedance.

Termination impedance apparatus with calibration circuit and method therefor

An integrated device (e.g., an integrated PCI bridge device) buffers received PCI bus strobe signals and distributes strobe signals for PCI receive data relative to the PCI data lines, enabling all PCI receive data to be latched using locally-generated PCI strobe signals generated based on the same PCI bus strobe signals. In addition, data line latch modules having primary and secondary flip-flops enable the PCI receive data to be held for an entire clock cycle, optimizing conversion between a PCI clock domain and a local clock domain of the PCI bridge device. A transmission circuit also can be configured to transmit data according to either double data rate (DDR) mode or quad data rate (QDR) mode in an efficient manner.

Arrangement for receiving and transmitting PCI-X data according to selected data modes

An integrated device (e.g., an integrated PCI bridge device), having configuration registers for storing configuration values, device logic for generating internal state values based on the configuration values, and a JTAG interface configured for receiving a serial input stream and outputting a serial output stream, further includes write logic and debug read logic. The write logic is configured for writing selected portions of the serial input stream into respective selected ones of the configuration registers, based on a detected input indicating a JTAG-based override. The debug read logic is configured, in response to a detected debug mode, for outputting selected internal state values for the serial output stream, based on selection values from the serial input stream and having been stored in a prescribed at least one of the selected configuration registers.

PCI bridge device configured for using JTAG scan for writing internal control registers and outputting debug state

An integrated device includes a voltage mode transmit driver for matching an output impedance to an output transmission line based on a binary code, an input termination module configured for matching an input impedance to an input transmission line based on an input impedance calibration value using thermometer-based decoding. The voltage mode transmit driver includes, for each differential output signal, a resistor network circuit having pull-up circuits and pull-down circuits for changing the voltage on the differential output signal, and having binary weighted resistance values relative to each other. The input termination module includes pull-up circuits and pull-down circuits having inverse hyperbolic resistance values relative to each other, and using thermometer-based decoding to ensure a linear change in input impedance during transitions in the input impedance calibration value. A calibration circuit generates the binary code and the input impedance calibration value based on replicas of the pull-up and pull-down circuits.

Voltage mode transceiver having programmable voltage swing and external reference-based calibration

Duplicate PCI bridge devices are configured for synchronous initializations based on shared initialization signals. A first of the PCI bridge devices is configured to rely on bus arbitration performed by the second PCI bridge device. The first PCI bridge device also is configured for modifying an address of a data transaction received via a PCI bus, and forwarding the data transaction with the modified address to the second PCI bridge device via a link distinct from the PCI bus.

Back to back connection of PCI host bridges on a single PCI bus

Memory transactions are carried out in an order that maximizes concurrency in a memory system such as a multi-bank interleaved memory system. Read data is collected in a buffer memory to be presented back to the bus in the same order as read transactions were requested. An adaptive algorithm groups writes to minimize overhead associated with transitioning from reading to writing into memory.

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Newton, MA, United States of America

Austen John Hypher