Intel Corporation

Motorola Corporation

Aurobindo Dasgupta

David Theodore Blaauw

David R Bearden

Mark E Schuelein

Sujal A Vora

Pradipto Mukherjee

Systems, methods, and apparatuses relating to enhanced matrix multiplier architecture are described. In one embodiment, an apparatus includes a matrix operations accelerator circuit having a two-dimensional grid of multiplier circuits; a first plurality of registers that represents a first two-dimensional matrix coupled to the matrix operations accelerator circuit; a second plurality of registers that represents a second two-dimensional matrix coupled to the matrix operations accelerator circuit; a decoder, of a core coupled to the matrix operations accelerator circuit, to decode a single instruction into a decoded single instruction; and an execution circuit of the core to execute the decoded single instruction to store each element of the first two-dimensional matrix from the first plurality of registers into a respective clocked flip-flop circuit of each multiplier circuit of the two-dimensional grid of multiplier circuits, store a first element of a first proper subset of elements of the second two-dimensional matrix from the second plurality of registers into a single first clocked flip-flop circuit coupled to a first proper subset of multiplier circuits of the two-dimensional grid of multiplier circuits, store a second element of the first proper subset of elements of the second two-dimensional matrix from the second plurality of registers into a single second clocked flip-flop circuit coupled to a second proper subset of multiplier circuits of the two-dimensional grid of multiplier circuits, multiply the first element of the first proper subset of elements from the single first clocked flip-flop circuit by a respective element from the clocked flip-flop circuit of each multiplier circuit of the first proper subset of multiplier circuits to generate a first plurality of resultants, and multiply the second element of the first proper subset of elements from the single second clocked flip-flop circuit by a respective element from the clocked flip-flop circuit of each multiplier circuit of the second proper subset of multiplier circuits to generate a second plurality of resultants.

Apparatuses, methods, and systems for enhanced matrix multiplier architecture

Embodiments disclosed herein provide sleep mode solutions for retaining state information while reducing power in a logic block.

Logic with state retentive sleep mode

The invention relates to a new method of guidance for routing of nets in an integrated circuit model wherein all nets are first approximately routed, as with Steiner routing, and victim nets with functional delay noise above predetermined thresholds are identified. Each victim net is then detail routed. For each victim net detail routed, a set of least noise aggressive neighboring nets is selected. Segments of those neighboring nets are assigned tracks adjacent to the victim net in such a way as to maximize utilization of the victim net's neighboring tracks, thereby reducing noise induced on the victim net and maximizing use of available space on the semiconductor. The process is then repeated until there are no additional victim nets, at which point the remaining nets are detail routed.

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Austin, TX, United States of America

Aurobindo Dasgupta