Marvell International Limited

Adaptec, Inc.

Qlogic Corporation

Aurelio J Cruz

Theodore Curt White

William W Dennin, Iii

Angel G Perozo

Ihn Kim

Takashi Asami

Khanh Trong Vu

A storage controller includes a memory controller that interfaces with memory that stores data. A first receive logic interface provides an interface to a host. A second receive logic interface provides an interface to a storage device. A power save module has a power save mode in which at least a clock of the memory controller is turned off while a clock for operating the first receive logic interface and the second receive logic interface is kept on.

Power save module for storage controllers

A method and system for transferring control information between a host and network processor is provided. The system includes, a snooping module that is coupled to a snooping memory bus; a network cache controller; a host process scheduler that communicates with the network cache controller; and a host cache controller that controls a host cache for transferring control information without polling. The method includes, invalidating a data block in a network cache, after a message is composed by the host processor; invalidating a status block in the network cache after the message is posted; and transferring control from the host processor to the network processor. The method also includes, invalidating a status segment in a network cache after data is transferred from a host cache to a network cache; and invalidating a status segment in the host cache after data has been injected to a network.

Method and system for host device event synchronization

A method and system using a storage controller for transferring data between a storage device and a host system is provided. The storage controller includes, a power save module that is enabled in a power save mode after a receive logic in the storage controller has processed all frames and during the power save mode at least a clock is turned off to save power while a clock for operating the receive logic is kept on to process any unsolicited frames that may be received by the receive logic. The storage controller operates in a single frame mode during the power save mode to process any unsolicited frames. Setting a bit in a configuration register for a processor enables the power save mode. The power save mode is enabled after a memory controller is in a self-refresh mode.

An integrated circuit, configured for connection to an SCSI bus includes a strobe assertion edge triggered glitch filter. Input data latches are controlled by the strobe assertion edge gated with a strobe enable signal and the inverted and delayed Q output of a flip-flop. Once a valid strobe assertion edge is detected, it is used latch data bus signals into the data latches. Following a defined delay period through a delay stage, the data latch strobe is masked from any further transition until the strobe enable signal is again affirmatively asserted by an SR latch. The masking period is defined upon receipt of a valid strobe assertion edge and maintained for a first period by the combination of the SR latch, a flip-flop and a delay stage. The latch strobe mask is maintained for a second period by a strobe masking extension circuit made up of series-connected flip-flops. The strobe mask extension period is determined by a sampling or reference clock frequency which propagates a signal through the flip-flops to subsequently cause the SR latch to affirmatively assert a strobe enable signal just before the expected arrival of a next valid assertion edge of the strobe signal.

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Aliso Viejo, CA, United States of America

Aurelio J Cruz